Thin Film Transistor Array Panel With 3D Gate Electrode Channel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In thin film transistor array panels, increasing the channel width to enhance display resolution while maintaining a reduced pixel size is challenging, as it often results in a decreased aperture ratio due to the increased area occupied by the thin film transistor.
Innovation Solution
The channel width of the thin film transistor is increased by utilizing both side surfaces of the gate electrode, allowing the semiconductor to cover both side surfaces and the upper surface of the gate electrode, without expanding the transistor's overall area, using an oxide semiconductor material such as zinc oxide or indium-gallium-zinc oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the channel width of the thin film transistor is increased to enhance display resolution, then the display resolution is improved, but the area occupied by the thin film transistor increases causing the aperture ratio to decrease
Solution Approach 1:
The patent extends the channel width from a single-plane configuration to a three-dimensional structure by utilizing both side surfaces of the gate electrode. The semiconductor layer is formed to cover the upper surface and both side surfaces of the gate electrode, effectively increasing the channel width without increasing the planar footprint of the transistor. This dimensional extension allows the channel to utilize vertical and lateral surfaces, thereby improving display resolution while maintaining the aperture ratio.
2Measurement precision
If the size of the pixel is decreased to increase resolution, then the display resolution is improved, but the area occupied by the thin film transistor must be maintained which becomes relatively larger
Solution Approach 1:
By forming the semiconductor layer to cover the side surfaces of the gate electrode, the patent creates a three-dimensional channel structure that increases the effective channel width within the same pixel area. This allows smaller pixels to maintain sufficient channel width for proper transistor operation, enabling higher display resolution without compromising transistor performance.
Solution Approach 2:
The patent changes the geometric parameters of the channel by utilizing the side surfaces of the gate electrode. The channel width is redefined to include contributions from both side surfaces in addition to the upper surface, effectively increasing the channel width parameter without increasing the planar area occupied by the transistor structure.
Data Source
AI summary
A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.