TFT Array Panel Manufacturing via Dual-Layer Conductive Film Patterning
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Solution Overview
Problem
Conventional methods for manufacturing thin film transistor array panels are inefficient, requiring multiple complex steps and potentially leading to unstable elements due to the complexity of film deposition and photolithography processes.
Innovation Solution
A method involving the sequential formation of gate lines, gate insulating layers, semiconductor layers, conductive films, and passivation layers, with specific photo-etching and removal steps to create pixel electrodes and columnar spacers, simplifying the process and reducing the number of photolithography steps while ensuring stable element formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple complex steps of film deposition and photolithography are used to manufacture TFT array panels, then the manufacturing precision and element stability can be improved, but the device complexity and production time increase significantly
Solution Approach 1:
The patent combines multiple photolithography steps into fewer steps by using a dual-layer conductive film structure (first and second conductive films) that are patterned together. The passivation layer is also patterned in conjunction with the conductive films, merging what would traditionally be separate photolithography processes into integrated steps, thereby reducing overall process complexity while maintaining manufacturing precision
Solution Approach 2:
The conductive films are divided into multiple layers (first conductive film and second conductive film) with different functions. The first conductive film forms the base electrode structure while the second conductive film creates the pixel electrode patterns. This segmentation allows each layer to be optimized independently and simplifies the patterning process by breaking down complex single-step patterning into manageable sequential steps
2Manufacturing precision
If multiple photolithography steps are performed sequentially, then the manufacturing precision of individual elements can be improved, but the productivity decreases due to increased process time
Solution Approach 1:
The first conductive film is deposited and patterned in advance to establish the base electrode structure and define the regions where subsequent layers will be formed. This preliminary structuring allows the second conductive film and passivation layer to be patterned more efficiently in later steps, as the underlying framework is already in place, reducing the complexity and time of subsequent photolithography operations
Solution Approach 2:
The passivation layer serves multiple functions: it provides electrical insulation, defines the pixel electrode boundaries, and protects the underlying conductive films. By designing the passivation layer pattern to simultaneously achieve insulation and structural definition, the patent eliminates the need for separate dedicated insulation layers or additional patterning steps, thereby improving productivity without sacrificing manufacturing precision
3Device complexity
If conventional manufacturing methods are used without separating source and drain electrodes, then the device complexity is reduced, but the reliability decreases due to potential disconnection issues
Solution Approach 1:
The source and drain electrodes are clearly separated by the passivation layer, which is patterned to expose only the necessary contact regions. This segmentation prevents unintended electrical connections between source and drain while maintaining clear definition of each electrode's function, thereby improving reliability without significantly increasing structural complexity
Solution Approach 2:
The passivation layer acts as an intermediary between the conductive films and the pixel electrode. It provides controlled electrical insulation while allowing specific regions to conduct, thereby preventing disconnection issues by ensuring proper electrical isolation where needed and maintaining conductive pathways where required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces production costs, and enhances the stability and reliability of thin film transistor array panels by separating source and drain electrodes using a passivation layer, contact assistants, and pixel electrodes, thereby improving productivity and preventing disconnection issues.
Implementation Method 1
depositing a gate insulating layer and a semiconductor layer in sequence on the gate line
Implementation Method 2
depositing a lower conductive film and an upper conductive film on the semiconductor layer
Implementation Method 3
photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer
Implementation Method 4
depositing a passivation layer
Implementation Method 5
photo-etching the passivation layer to expose first and second portions of the upper conductive film
Data Source
AI summary
A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper conductive film on the semiconductor layer; photo-etching the upper conductive film, the lower conductive film, and the semiconductor layer; depositing a passivation layer; photo-etching the passivation layer to expose first and second portions of the upper conductive film; removing the first and the second portions of the upper conductive film to expose first and second portions of the lower conductive film; forming a pixel electrode on the first portion of the lower conductive film; removing the second portion of the lower conductive film to expose a portion of the semiconductor layer; and forming a columnar spacer on the exposed portion of the semiconductor layer.