Thin Film Transistor Array Panel Etch Stop Integration
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Solution Overview
Problem
The manufacturing process of etch stopper type thin film transistors for display devices is complex and requires additional steps, which complicates the production and reduces reliability and charge mobility compared to etch back type transistors.
Innovation Solution
A thin film transistor array panel design that includes etch stop members formed on amorphous silicon semiconductors, with a simplified manufacturing method using photolithography to pattern and etch the etch stop and semiconductor layers simultaneously, reducing the number of photolithography processes and enhancing charge mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If etch stopper type thin film transistor manufacturing process is used, then reliability and charge mobility are improved, but manufacturing process complexity increases due to additional etch stopper formation steps
Solution Approach 1:
The patent combines the etch stopper layer and semiconductor layer into a single integrated structure. The etch stopper is formed as an intrinsic or lightly-doped silicon layer within the semiconductor layer itself, rather than as a separate additional layer. This merging eliminates the need for separate etch stopper formation steps while maintaining the protective function during subsequent etching processes, thus improving reliability without increasing manufacturing complexity.
Solution Approach 2:
The semiconductor layer serves multiple functions: it provides the active semiconductor region for transistor operation and simultaneously functions as the etch stopper layer. The intrinsic or lightly-doped portion of the semiconductor layer acts as both the channel region and the protective etch stop during data wire layer etching, eliminating the need for a dedicated etch stopper layer and simplifying the manufacturing process.
2Ease of manufacture
If etch back type thin film transistor manufacturing process is used, then manufacturing process is simplified, but reliability and charge mobility deteriorate
Solution Approach 1:
The patent merges the etch stopper function into the semiconductor layer by forming an intrinsic or lightly-doped silicon region within it. This eliminates the need for separate etch stopper formation steps required in etch stopper type transistors, achieving process simplicity comparable to etch back type, while maintaining the reliability benefits through proper etch selectivity and device structure design.
3Reliability
If additional photolithography processes are used to form etch stopper, then etch stopper type transistor is formed, but manufacturing time and productivity are reduced
Solution Approach 1:
The etch stopper layer and semiconductor layer are formed as an integrated structure using a single photolithography and etching process sequence. The intrinsic or lightly-doped silicon layer is formed simultaneously with the semiconductor layer, eliminating the need for additional photolithography steps dedicated to etch stopper formation, thus maintaining productivity while achieving reliable etch stopper type transistor characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the manufacturing process of etch stopper type thin film transistors, improving their reliability and charge mobility, achieving about 0.8 V/cm2sec, higher than the etch back type, while maintaining stability characteristics.
Implementation Method 1
A simplified manufacturing method using photolithography to pattern and etch the etch stop and semiconductor layers simultaneously
Data Source
AI summary
A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using photolithography; ashing and partially removing a photoresist film pattern used in the patterning of the etch stop and semiconductor layers; etching the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members; depositing ohmic contact and data metal layers onto the etch stop members, etching the ohmic contact and data metal layers at the same time using photolithography to form data lines having source and drain electrodes, and ohmic contact members below the source and drain electrodes; forming a passivation layer on the data lines and drain electrodes; and forming pixel electrodes on the passivation layer.