TFT Array Panel Etching Protrusion Control
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Solution Overview
Problem
The existing methods for manufacturing thin film transistor array panels result in increased skew during etching of the data metal layer, leading to protrusions on the semiconductor layer's side wall, which are difficult to minimize.
Innovation Solution
A method involving sequential formation of gate and data metal layers, followed by specific etching processes using photosensitive films with different thicknesses and ashing steps to form undercut structures, reducing the protrusion of the semiconductor layer's side wall relative to the data line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the data metal layer is etched using conventional methods, then the etching process is simple and fast, but the side wall of the semiconductor layer protrudes past the side wall of the data metal layer
Solution Approach 1:
The etching process is divided into multiple stages: first forming an initial data metal pattern with a photosensitive film, then performing a second etching step to create the final data line. This segmentation allows precise control of the etching depth and profile to minimize semiconductor layer protrusion.
Solution Approach 2:
An undercut structure is formed in the data metal layer before the final etching step. This preliminary action creates a recess that compensates for the expected protrusion of the semiconductor layer, ensuring better alignment between the semiconductor layer side wall and data line side wall.
2Manufacturing precision
If the photosensitive film thickness is increased to reduce protrusion, then the alignment precision improves, but the etching time increases
Solution Approach 1:
The photosensitive film is formed with different thicknesses in different regions: a first thickness in the channel region and a second thickness (greater than the first) in the data line region. This local quality variation allows precise control of etching depth in critical areas without unnecessarily increasing etching time across the entire structure.
Solution Approach 2:
The photosensitive film thickness is optimized to provide just enough coverage to control the protrusion, rather than uniformly thick coverage everywhere. This partial action approach achieves the necessary precision while minimizing etching time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the protrusion of the semiconductor layer's side wall by 18% compared to traditional methods, while also reducing etching time by 17%, improving the manufacturing efficiency and quality of the thin film transistor array panel.
Implementation Method 1
forming a first photosensitive film pattern that includes a first part and a second part that is thicker than the first part, on the upper data metal layer
Implementation Method 2
forming a second photosensitive film pattern by ashing the first photosensitive film pattern
Data Source
AI summary
A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.