TFT Array Panel Single Mask Etching Stop Layer
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Solution Overview
Problem
The manufacturing process of thin film transistor (TFT) array panels for liquid crystal displays using oxide semiconductors is costly and complex due to the need for multiple masks and etching preventing layers, which increase production costs and complexity.
Innovation Solution
A TFT array panel design that incorporates an etching stop layer and insulating layer formed simultaneously using a single mask, with the etching stop layer and insulating layer disposed on specific portions of the semiconductor and gate insulating layer, allowing for the formation of source and drain electrodes with reduced complexity and cost, using materials like GIZO, ZTO, or IZO as oxide semiconductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching preventing layer and mask are formed separately for oxide semiconductor TFTs, then etching damage to the oxide semiconductor is reduced, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent combines the etching preventing layer and insulating layer into a single integrated layer structure. The etching preventing layer is formed as part of the insulating layer deposition process, eliminating the need for separate formation steps. This merging reduces the number of masks required from two to one, thereby simplifying the manufacturing process while maintaining etching protection functionality.
Solution Approach 2:
The insulating layer is designed to serve multiple functions simultaneously: it provides electrical insulation between conductive layers and acts as an etching preventing layer during source and drain electrode formation. This multi-functionality eliminates the need for a dedicated etching preventing layer, reducing process complexity and manufacturing cost while maintaining reliability.
2Manufacturing precision
If multiple masks are used for forming etching preventing layer and insulating layer, then layer precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the formation of etching preventing layer and insulating layer into a single deposition step using one mask. The mask pattern is designed to define both layers simultaneously, reducing the number of photolithography and etching cycles required. This approach maintains adequate layer precision while significantly reducing manufacturing cost by eliminating redundant process steps.
Solution Approach 2:
The insulating layer is deposited to cover the entire semiconductor region before the source and drain electrode formation. This preliminary coverage provides built-in etching protection for the oxide semiconductor channel region, eliminating the need for subsequent etching preventing layer formation and reducing the total number of masks required.
Data Source
AI summary
A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer.