Thin Film Transistor Array Panel Using Fluorinated Silicon Oxide Interface
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Solution Overview
Problem
Thin film transistors using amorphous silicon have low charge mobility and complex manufacturing processes, while polysilicon requires more processes and has high power consumption due to high threshold voltage, limiting their performance in display devices.
Innovation Solution
A thin film transistor array panel utilizing a p-type oxide semiconductor material with a fluorinated silicon oxide interface layer, which reduces the threshold voltage and increases carrier mobility, thereby lowering power consumption and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as semiconductor material, then manufacturing process is relatively simple, but charge mobility is low
Solution Approach 1:
The patent changes the material parameter from conventional silicon-based semiconductors to oxide semiconductor (IGZO), fundamentally altering the semiconductor's electrical properties to achieve high charge mobility while maintaining low-temperature processing capability
Solution Approach 2:
The patent employs a composite structure combining oxide semiconductor layer with specific interface layers and gate insulating layers, creating a multi-layer system that optimizes both electrical performance and manufacturing feasibility
2Speed
If polysilicon is used as semiconductor material, then charge mobility is high, but manufacturing requires more processes including crystallizing silicon
Solution Approach 1:
The patent changes the crystallization temperature parameter by using oxide semiconductor that can be processed at low temperatures (below 450°C), eliminating the need for complex high-temperature crystallization processes required by polysilicon
Solution Approach 2:
The patent uses a semiconductor material that can be deposited as a thin film in a single step without requiring subsequent crystallization treatments, effectively replacing the multi-step polysilicon process with a simpler, more economical process
3Speed
If polysilicon is used as semiconductor material, then charge mobility is high, but threshold voltage is high causing high power consumption
Solution Approach 1:
The patent changes the electrical parameter of threshold voltage by using oxide semiconductor material, which inherently provides lower threshold voltage compared to polysilicon, thereby reducing power consumption while maintaining high charge mobility
Solution Approach 2:
The patent introduces an interface layer with specific properties between the gate insulating layer and semiconductor layer, creating a localized region that optimizes electrical characteristics and reduces threshold voltage in the critical interface region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a p-type oxide semiconductor with a fluorinated silicon oxide interface layer decreases the threshold voltage and enhances transistor efficiency, reducing power consumption and improving performance in display devices.
Implementation Method 1
The interface layer includes a fluorinated silicon oxide
Data Source
AI summary
A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material.