Thin Film Transistor Array Panel Mask Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of liquid crystal displays (LCDs) is costly due to the high number of optical masks required, which increases production expenses.
Innovation Solution
A thin film transistor array panel design that includes a first and second passivation layer with a pixel electrode coupled to the thin film transistor through a contact hole, where the first part of the contact hole in the common electrode is larger than the second part in the second passivation layer, allowing for a reduced number of masks in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple optical masks are used in the manufacturing process to form field generating electrodes, then the precision and functionality of the display panel are improved, but the manufacturing cost and process complexity increase
Solution Approach 1:
The patent combines the formation of the common electrode and pixel electrode into a single simultaneous etching process. The etching solution penetrates through both the first and second passivation layers at the same time, creating both electrodes through one manufacturing step rather than requiring separate masking and etching processes for each electrode, thereby reducing the number of optical masks needed
Solution Approach 2:
The single etching solution serves multiple functions: it etches through the first passivation layer to form the common electrode, etches through the second passivation layer to form the pixel electrode, and creates the necessary contact holes in both layers simultaneously. This multi-functional approach eliminates the need for multiple specialized masking steps
2Manufacturing precision
If multiple optical masks are used in the manufacturing process, then the manufacturing precision is improved, but the production time increases
Solution Approach 1:
The patent merges multiple sequential operations (etching common electrode, etching pixel electrode, forming contact holes) into a single simultaneous etching operation. The etching solution is applied once and processes all required features in parallel, dramatically reducing the total production time compared to sequential processing with multiple masks
Solution Approach 2:
The passivation layers are designed with pre-determined thicknesses and material compositions that allow the etching solution to penetrate at controlled rates, ensuring that both electrodes are formed with proper dimensions and alignment in a single pass without requiring multiple iterative masking steps
Data Source
AI summary
A thin film transistor array panel is provided. A thin film transistor is positioned on a substrate. A first passivation layer is positioned on the thin film transistor. A common electrode is positioned on the first passivation layer. A second passivation layer positioned on the common electrode. A pixel electrode is positioned on the second passivation layer. The pixel electrode is coupled to the thin film transistor through a first contact hole penetrating the first passivation layer, the common electrode, and the second passivation layer. A first part of the first contact hole formed in the common electrode is larger than a second part of the first contact hole formed in the second passivation layer.