TFT Array Panel Reducing Mask Processes in OLED Displays
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Solution Overview
Problem
The manufacturing process of active matrix OLED displays using multiple masks increases process time and production costs due to the complexity of photolithography processes.
Innovation Solution
The proposed solution involves a TFT array panel structure and manufacturing method that includes a substrate with a semiconductor having source and drain areas, a gate insulating layer, and electrodes, with offset areas to reduce leakage current, and a method of stacking layers and etching using a photosensitive film pattern to form a metal pattern and gate electrode, followed by doping and forming contact holes for source and drain electrodes, thereby reducing the number of mask processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used in photolithography process, then manufacturing precision is improved, but process time and production cost increase
Solution Approach 1:
The patent combines multiple photolithography mask processes into a single mask process. The TFT array panel structure is designed so that the gate electrode, source electrode, and drain electrode can be formed simultaneously using one mask pattern, eliminating the need for separate mask processes for each electrode. This merging of processes directly reduces process time while maintaining manufacturing precision through the integrated design.
Solution Approach 2:
The single mask used in the photolithography process serves multiple functions: it defines the gate electrode pattern, source electrode pattern, and drain electrode pattern simultaneously. The mask structure is designed with multi-functional regions that create different electrode patterns from a single exposure, making the mask process universal for forming all three electrodes that would traditionally require separate masks.
2Manufacturing precision
If multiple masks are used in photolithography process, then manufacturing precision is improved, but production cost increases
Solution Approach 1:
The patent merges multiple mask processes into one, directly reducing the cost of mask materials, mask alignment equipment usage, and process overhead. The single mask approach eliminates the need for multiple mask sets and reduces the complexity of mask alignment procedures, thereby lowering production costs while maintaining the precision required for TFT electrode formation.
Solution Approach 2:
The patent discards the traditional multi-mask approach and recovers resources by using a single mask that can be processed more efficiently. The simplified process reduces waste in terms of mask materials, chemical etchants, and processing time, leading to cost recovery and improved manufacturing efficiency.
3Reliability
If offset areas are added to reduce leakage current, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by adding offset areas specifically in regions where leakage current is problematic, rather than uniformly increasing complexity throughout the entire device. The offset areas are strategically positioned between the gate electrode and source/drain electrodes to provide electrical isolation where needed, while leaving other regions simple. This localized approach improves reliability by reducing leakage current without unnecessarily increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of mask processes, shortening the manufacturing time and cost of OLED displays by simplifying the production process while maintaining the quality of the TFT array panel and OLED display.
Implementation Method 1
forming a photosensitive film pattern having a first portion and a second portion having a thickness smaller than that of the first portion on the metal layer, forming a metal pattern, a gate insulating layer, and a semiconductor by etching the metal layer, the insulating layer, and the polysilicon layer using the photosensitive film pattern as a mask
Implementation Method 2
forming a source area and a drain area by doping semiconductor conductive impurities through the contact hole
Data Source
AI summary
A thin film transistor array panel includes a substrate, a semiconductor that is positioned on the substrate and that has a source area, a drain area, and a channel area, a gate insulating layer that is positioned on the semiconductor, a gate electrode that is positioned on the gate insulating layer and that overlaps the channel area, a first interlayer insulating layer that is positioned on the gate electrode and that has contact holes that expose the source area and the drain area, respectively, of which the source area and the drain area have a same plane pattern as that of the contact holes, and a source electrode and a drain electrode that are positioned on the first interlayer insulating layer and that are connected to the source area and the drain area, through the contact holes, respectively.