Thin Film Transistor Array Panel with Protruded Ohmic Contacts

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Solution Overview

Problem

In the manufacturing of liquid crystal display (LCD) thin film transistor arrays, metal from the source and drain electrodes can contaminate the channel, degrading the performance of the transistors due to improper etching processes.

Innovation Solution

The design includes a semiconductor layer with a channel part that does not overlap the source and drain electrodes, and the use of ohmic contacts with specific edge protrusions to prevent metal contamination, along with a protection layer that can be etched by the same etchant as the electrodes, ensuring precise etching and minimizing channel contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal layers are etched to form source and drain electrodes, then electrode connectivity is achieved, but metal contamination flows into the channel degrading transistor performance

Engineering Contradiction:
Improvetransistor performanceVSAvoidmetal contamination
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A protection layer made of silicon oxide is introduced as an intermediary between the metal electrode layers and the semiconductor channel. This protection layer is selectively removed only at the channel region, allowing the channel to be exposed while the source and drain electrode regions remain protected from etching. This prevents metal contamination in the channel while maintaining electrode connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The protection layer is deposited on the metal layers before the etching process begins. This preliminary protective coating prevents metal from flowing into the channel during subsequent etching operations. The protection layer is then selectively removed at the channel region to allow proper electrode formation without contamination.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If etching process is performed to form electrodes, then electrode structure is created, but channel contamination occurs due to metal flow

Engineering Contradiction:
Improveelectrode formation precisionVSAvoidchannel contamination
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The protection layer is selectively removed only at the channel region while maintaining the protection coating at the source and drain electrode regions. This creates local differences in protection: the channel area is exposed for proper electrode formation, while the electrode areas remain protected from etching-induced metal contamination. This local quality approach enables precise electrode formation without channel contamination.

Inventive Principle:
Principle #3Local quality

3Reliability

If source and drain electrodes are formed overlapping the semiconductor layer, then electrical connectivity is achieved, but metal contamination degrades the channel

Engineering Contradiction:
Improvetransistor reliabilityVSAvoidchannel cleanliness
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The protection layer serves as an intermediary that prevents direct contact between the metal electrode material and the semiconductor channel during the etching process. By depositing this protective silicon oxide layer on the metal layers before etching, and then selectively removing it only at the channel region, the invention ensures that metal contamination is prevented while maintaining proper electrical connectivity through the formed electrodes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10128274B2Thin film transistor array panel and a method for manufacturing the same
Publication Date: 2018.11.13 SAMSUNG DISPLAY CO LTD
  • US10128274B2 patent drawing
  • US10128274B2 patent drawing
  • US10128274B2 patent drawing

AI summary

A thin film transistor array panel including: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode overlapping the semiconductor layer, and a gate electrode overlapping the semiconductor layer; and a first ohmic contact disposed between the semiconductor layer and the source electrode and a second ohmic contact disposed between the semiconductor layer and the drain electrode. The semiconductor layer includes a channel part that does not overlap the source electrode and the drain electrode. The first ohmic contact includes a first edge and the second ohmic contact includes a second edge. The first and second edges face each other across the channel part of the semiconductor layer. The first edge of the first ohmic contact is protruded from the source electrode toward the channel part and the second edge of the second ohmic contact is protruded from the drain electrode toward the channel part.