Thin Film Transistor Array Panel S-Factor Optimization
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Solution Overview
Problem
Existing thin film transistor array panels for OLED displays face challenges in achieving optimal S-factor characteristics for both switching and driving transistors, which affect the display's luminance uniformity and operational speed.
Innovation Solution
The solution involves a thin film transistor array panel design with a substrate featuring driving and switching transistors, where the driving transistor includes an oxide layer between the semiconductor and gate insulating layer, while the switching transistor does not, and a manufacturing method that includes crystallizing an amorphous silicon layer, forming an oxide layer, and patterning semiconductors with photolithography and etching processes to achieve distinct S-factor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an oxide layer is added between the semiconductor and gate insulating layer for driving transistors, then S-factor characteristics are improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent applies different structures to different transistor types: driving transistors include an oxide layer between the semiconductor and gate insulating layer to improve S-factor characteristics, while switching transistors do not include this oxide layer. This local differentiation allows each transistor type to have optimized characteristics for its specific function without unnecessary complexity in other areas.
2Reliability
If selective oxide layer formation is implemented for different transistor types, then S-factor characteristics are optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms a first oxide layer on the semiconductor layer before pattern separation, then uses this pre-formed oxide layer as a basis for subsequent selective removal and formation processes. This preliminary action simplifies the overall manufacturing process by establishing a common foundation before differentiation, reducing the precision requirements for subsequent steps.
Solution Approach 2:
The patent introduces a plasma treatment step as an intermediary process between oxide layer formation and pattern separation. This plasma treatment modifies the oxide layer properties to facilitate selective removal in subsequent steps, acting as a mediator that enables precise differentiation between driving and switching transistor regions without requiring extremely high pattern alignment precision.
3Illumination intensity
If different S-factor characteristics are achieved for driving and switching transistors, then luminance uniformity is improved, but operational speed may be compromised
Solution Approach 1:
The patent optimizes S-factor characteristics locally for driving transistors by adding an oxide layer, which improves luminance uniformity. Switching transistors maintain their original structure to preserve fast operational speed. This localized optimization allows the system to achieve good luminance uniformity without compromising the operational speed of switching transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design and manufacturing method allow for a thin film transistor array panel with improved S-factor characteristics, enhancing luminance uniformity and operational speed by selectively optimizing the oxide layer thickness and plasma treatment for each transistor type.
Implementation Method 1
The amorphous silicon layer is crystallized to form a polysilicon layer
Implementation Method 2
An oxide layer is formed on the polysilicon layer
Data Source
AI summary
A thin film transistor array panel includes a plurality of pixels on a substrate. Each pixel of the plurality of pixels includes a driving and a switching thin film transistor. The driving thin film transistor includes a first semiconductor including first source and drain regions, a first gate electrode overlapping the first semiconductor, a gate insulating layer between the first semiconductor and the first gate electrode, an oxide layer between the first semiconductor and the gate insulating layer, and first source and drain electrodes. The switching thin film transistor includes a second semiconductor including second source and drain regions, a second gate electrode overlapping the second semiconductor, and second source and drain electrodes. The switching thin film transistor includes the gate insulating layer between the second semiconductor and the second gate electrode. The gate insulating layer contacts an upper portion of the second semiconductor.