TFT Array Substrate Layout With Shared Transparent Electrode Patterning

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Solution Overview

Problem

The production of thin film transistor array substrates for electronic paper displays is hindered by the need for multiple photomask processes, which increases cycle time and costs, especially for lower resolution requirements.

Innovation Solution

A manufacturing method for a thin film transistor array substrate that forms a transparent electrode layer on top of the second metal layer, allowing it to be patterned using the same photoresist layer as the second metal layer, thereby reducing the number of photomask processes required and enabling the second portion of the transparent electrode layer to serve as an etch stop layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If seven or eight photomask processes are used to pattern gate, gate insulator, semiconductor film, source/drain, passivation layer, overcoat layer, and transparent electrode layer, then the array function for driving electronic ink layer is completed, but the cycle time for producing the thin film transistor array substrate increases and manufacturing cost increases

Engineering Contradiction:
Improvearray function completionVSAvoidcycle time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines the patterning of the transparent electrode layer with the patterning of the second metal layer by forming the transparent electrode layer after the second metal layer is formed, allowing both layers to be patterned using the same photoresist layer. This merging of operations reduces the total number of photomask processes from seven or eight to fewer steps, thereby shortening the production cycle time while still achieving the required array function for driving the electronic ink layer

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The photoresist layer serves multiple functions: it is used for patterning the second metal layer and also for patterning the transparent electrode layer. This multi-functional use of the same photoresist layer eliminates the need for separate photomask processes for each layer, reducing both time and cost while maintaining the complete array function

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If seven or eight photomask processes are used for patterning multiple layers, then complete array function is achieved, but manufacturing cost increases due to expensive photomask

Engineering Contradiction:
Improvearray function completionVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the patterning operations for the second metal layer and transparent electrode layer into a single photomask process. By forming the transparent electrode layer after the second metal layer, both layers can be patterned simultaneously using the same photoresist layer, reducing the number of expensive photomasks required from seven or eight to fewer, thereby lowering manufacturing cost while maintaining complete array function

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The same photoresist layer is used universally for patterning both the second metal layer and the transparent electrode layer. This multi-functional application of a single photomask process eliminates redundant expensive photomask steps, reducing manufacturing cost while ensuring the complete array function is achieved

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230387133A1Thin film transistor array substrate and manufacturing method thereof
Publication Date: 2023.11.30 E INK HLDG INC
  • US20230387133A1 patent drawing
  • US20230387133A1 patent drawing
  • US20230387133A1 patent drawing

AI summary

A TFT array substrate includes a bottom plate, a first metal layer, an insulating layer, a semiconductor layer, a second metal layer, and a transparent electrode layer. The first metal layer is located on the bottom plate. The insulating layer covers the bottom plate and the first metal layer. The semiconductor layer is located on the insulating layer and overlaps a first portion of the first metal layer. The second metal layer has a first portion on the semiconductor layer and a second portion on the insulating layer, and the second portion of the second metal layer overlaps a second portion of the first metal layer. A first portion of the transparent electrode layer is disposed along the first portion of the second metal layer, and a second portion of the transparent electrode layer is disposed along the second portion of the second metal layer.