TFT Array Substrate 3-Mask Process Merging Pixel and Data Lines
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Solution Overview
Problem
The conventional 4-Mask process for manufacturing TFT array substrates is complex, costly, and time-consuming, limiting the efficiency and yield of thin film transistor liquid crystal displays.
Innovation Solution
A 3-Mask process is employed, involving specific layer deposition and photolithography steps to form common electrode lines, gate electrodes, source and drain electrodes, via holes, and connections for data lines and pixel electrodes, reducing the number of processes and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a 4-Mask process is used to manufacture TFT array substrate, then the manufacturing precision and reliability are maintained, but the device complexity and production time increase significantly
Solution Approach 1:
The patent merges the formation of pixel electrodes and data lines into a single photolithography step by depositing both materials simultaneously and patterning them together. This combines what were previously separate processing steps into one unified operation, reducing the total mask count from 4 to 3 while maintaining pattern precision through coordinated deposition and single-step patterning
2Manufacturing precision
If a 4-Mask process is used to manufacture TFT array substrate, then the manufacturing precision is maintained, but the production cost increases
Solution Approach 1:
The patent reduces production cost by merging the pixel electrode and data line formation into a single photolithography step. This eliminates one mask alignment step and reduces the total number of photolithography processes from 4 to 3, directly lowering manufacturing costs while maintaining pattern precision through simultaneous deposition and unified patterning
3Manufacturing precision
If a 4-Mask process is used to manufacture TFT array substrate, then the manufacturing precision is maintained, but the productivity decreases
Solution Approach 1:
The patent improves productivity by combining the formation of pixel electrodes and data lines into one photolithography step. This reduces the total number of photolithography processes from 4 to 3, shortening the production cycle and increasing throughput while maintaining pattern precision through coordinated deposition and single-step patterning of both structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 3-Mask process decreases production costs and increases efficiency by simplifying the manufacturing process, reducing the complexity and duration of the TFT array substrate production.
Implementation Method 1
depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer
Implementation Method 2
depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer
Implementation Method 3
performing a first photolithograph process, and form common electrode lines, gate lines, a gate electrode, a source electrode, a drain electrode and a channel
Implementation Method 4
faun a first via hole in the passivation layer located above the source electrode and a second via hole in the passivation layer located above the drain electrode
Data Source
AI summary
The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.