TFT Array Substrate with Capacitance Compensating Lines
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Solution Overview
Problem
In large-sized and high-resolution LCD panels, signal distortion due to RC delay and overheating issues in driver ICs are unresolved, and alternative pixel layouts to mitigate these problems reduce the aperture ratio and regularity of photomask patterns, leading to misalignment and light leakage.
Innovation Solution
A TFT array substrate design with capacitance compensating lines and shielding patterns that balance parasitic capacitances between pixels, maintaining the aperture ratio and reducing misalignment, where TFTs are connected to adjacent data lines and capacitance compensating lines are used to compensate for parasitic capacitances, and shielding patterns are employed to prevent light leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternative pixel layout is used to reduce driver IC overheating and RC delay, then display quality is improved, but aperture ratio and display area size are reduced
Solution Approach 1:
The invention segments the pixel structure into distinct first and second pixel rows with different TFT connection patterns. First pixel rows use conventional connections while second pixel rows use alternative connections, allowing the system to benefit from both approaches without sacrificing overall aperture ratio.
Solution Approach 2:
The invention applies different connection patterns to different regions (pixel rows) based on local requirements. Specifically, second pixel rows use alternative TFT connections to reduce parasitic capacitance and prevent overheating, while first pixel rows maintain conventional connections, creating localized optimization without global compromise.
2Reliability
If alternative pixel layout is used to reduce driver IC overheating, then reliability is improved, but photomask pattern regularity is reduced leading to misalignment
Solution Approach 1:
The invention divides the pixel array into alternating rows with different connection patterns, where second pixel rows use alternative connections to reduce heat while first pixel rows maintain conventional patterns for manufacturing regularity. This segmentation allows heat management benefits without sacrificing overall photomask alignment.
Solution Approach 2:
Instead of applying alternative connections to all pixels (which would cause alignment issues), the invention inverts the approach by applying conventional connections to every other row (first pixel rows), thereby maintaining manufacturing regularity while still achieving heat reduction benefits in the alternative rows.
3Device complexity
If TFTs are connected to adjacent two data lines alternatively, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The invention applies alternative TFT connections to specific regions (second pixel rows) where parasitic capacitance reduction is most beneficial, while maintaining conventional connections in first pixel rows. This localized application optimizes capacitance balance without unnecessarily increasing overall device complexity.
Solution Approach 2:
The invention segments the pixel array into two types of rows with different connection patterns, allowing the alternative connection structure to be implemented in a controlled manner that balances parasitic capacitance while managing device complexity through systematic division.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces inconsistent parasitic capacitances and maintains the aperture ratio and display area size, preventing bright/dark lines and overheating issues while improving display uniformity and reducing misalignment.
Implementation Method 1
parasitic capacitances between pixels are balanced and thus inconsistent parasitic capacitances between pixels are reduced
Data Source
AI summary
A thin film transistor (TFT) array substrate including a substrate, a plurality of scan lines disposed on the substrate, a plurality of data lines disposed on the substrate, and a plurality of pixels arranged in array on the substrate is provided. Each scan line is connected to a row of pixels. Each pixel includes a TFT and a pixel electrode, wherein the pixel electrode is connected to one of the scan lines and one of the data lines through the TFT. In the same column of pixels, the TFTs are connected to two adjacent data lines alternatively and aligned in the column direction. At least one of the pixels further includes a capacitance compensating line. In the pixel having the capacitance compensating line, the TFT is connected to one of the adjacent two data lines, and the capacitance compensating line is connected to the other one.