Thin Film Transistor Array Substrate with Etch Stop Layer
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Solution Overview
Problem
Existing thin film transistor array substrates face issues with undesirable parasitic capacitance and reduced driving speed due to overlapping source and drain electrodes with the gate electrode, leading to longer channel regions and increased fabrication costs and time.
Innovation Solution
The substrate design and fabrication method involve forming source and drain electrodes that do not overlap the gate electrode, with an etch stop layer positioned between them, allowing for a shorter channel region and reduced parasitic capacitance, achieved through a rear exposure process using the gate electrode as a mask, thereby enhancing performance and reducing fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source and drain electrodes overlap the gate electrode, then the channel region length is increased, but parasitic capacitance increases and driving speed decreases
Solution Approach 1:
The patent extracts the overlapping region between source/drain electrodes and gate electrode by introducing an etch stop layer that defines the channel region boundaries. The source and drain electrodes are positioned to extend beyond the etch stop layer, preventing overlap with the gate electrode and eliminating the harmful parasitic capacitance while maintaining the necessary channel length for device operation.
Solution Approach 2:
The etch stop layer serves as an intermediary element between the source/drain electrodes and the gate electrode. It defines the channel region and physically separates the source/drain electrodes from overlapping with the gate electrode, thereby mediating the spatial relationship to eliminate parasitic capacitance while preserving the functional channel region.
2Manufacturing precision
If multiple masking procedures are used to define channel region, then manufacturing precision is improved, but fabrication time and cost increase
Solution Approach 1:
The patent merges the channel region definition function into the etch stop layer formation process. The etch stop layer is patterned to define the channel region boundaries, combining what would traditionally require separate masking steps into a single integrated process. This reduces fabrication complexity and time while maintaining the precision needed for channel region definition.
Solution Approach 2:
The etch stop layer performs multiple functions: it defines the channel region boundaries, serves as a stopping layer for subsequent etching processes, and prevents source/drain electrode overlap with the gate electrode. This multi-functionality eliminates the need for additional dedicated masking procedures, reducing fabrication time and cost while maintaining manufacturing precision.
Data Source
AI summary
A thin film transistor array substrate is discussed. The thin film transistor array substrate includes, according to one embodiment, gate and data lines crossing each other, a gate insulation film, a gate electrode, an active layer, an etch stop layer formed on the active layer to define a channel region of the active layer, and a source electrode and a drain electrode formed on the active layer. The etch stop layer is between the source and drain electrodes spaced apart from the etch stop layer. The source electrode and the drain electrode include a first electrode layer and a second electrode layer disposed on the first electrode. The first electrode layer is formed from a dry-etchable material and the second electrode layer is formed from a wet-etchable material.