Thin Film Transistor Array Substrate Single Lithography Process
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Solution Overview
Problem
The manufacturing process of thin film transistor array substrates is costly and time-consuming due to the multiple lithography steps required, which increases the complexity and expense of producing layered structures for display devices like LCDs and OLEDs.
Innovation Solution
A method for manufacturing a thin film transistor array substrate that involves forming a gate line with a lower and upper film, a gate insulating layer, a semiconductor layer, and ohmic contact layer, where the data line, source electrode, and drain electrode are formed using a single photoresist coating process, reducing the number of lithography steps by controlling the photoresist height to match the semiconductor layer height, and incorporating a passivation layer with a contact hole for the pixel electrode, thereby optimizing the structure for reduced parasitic capacitance and improved display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple lithography steps are used to form the layered structure of gate lines, data lines, and electrodes, then the structural precision and layer alignment are improved, but the manufacturing cost and production time increase
Solution Approach 1:
The patent combines multiple lithography steps into a single lithography process by using a thick photoresist layer that is patterned to form gate lines, data lines, and electrode structures simultaneously. This merging of steps reduces production time while maintaining the necessary structural precision through the thick photoresist mask that protects underlying layers during etching.
Solution Approach 2:
The patent applies preliminary action by forming a thick photoresist layer before patterning, which serves as a robust mask for subsequent etching steps. This preliminary thick photoresist formation enables single-step lithography to achieve what would otherwise require multiple lithography steps, thereby reducing production time while maintaining precision.
2Manufacturing precision
If multiple lithography steps are used to form the layered structure, then the structural precision and layer alignment are improved, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple lithography steps into one by using a thick photoresist layer that can be patterned in a single step to define gate lines, data lines, and electrodes. This reduces the number of expensive lithography operations required while maintaining the necessary alignment precision through the thick mask's ability to protect all required structures simultaneously.
3Productivity
If the photoresist height is controlled to match the semiconductor layer height, then the number of lithography steps is reduced, but the manufacturing precision of electrode heights may be affected
Solution Approach 1:
The patent changes the parameter of photoresist thickness to be equal to or greater than the semiconductor layer thickness, which enables single-step lithography to achieve proper electrode height control. This parameter change allows the photoresist to serve as both a pattern mask and a height reference, reducing the number of lithography steps while maintaining electrode height precision.
Data Source
AI summary
A thin film transistor array substrate includes a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an upper film thicker than the lower film, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer formed on the semiconductor layer, a data line electrically connected to a source electrode and a drain electrode formed on the ohmic contact layer, the lower film of the gate line is in contact with the gate insulating layer at a crossing portion of the gate line and the data line and the heights of the source electrode and the drain electrode are substantially the same as or less than a height of the semiconductor layer.