TFT Array Substrate Manufacturing via Merged Photolithography
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Solution Overview
Problem
The high manufacturing costs of fringe-field switching mode liquid crystal display devices are attributed to the need for multiple photolithography processes in producing thin-film transistor array substrates, which complicates process control and increases the expense of half-tone masks.
Innovation Solution
A method for manufacturing a thin-film transistor array substrate that reduces the number of photolithography processes by forming a gate electrode, source and drain electrodes, pixel electrode, and counter electrode using a sequence of metal and transparent conductive layers, eliminating the need for a half-tone mask and integrating processes to achieve a simpler and cost-effective production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography processes are used to form gate electrode, source and drain electrodes, contact holes, and pixel electrode in FFS mode liquid crystal display devices, then the manufacturing precision and device performance are improved, but the manufacturing cost and process complexity increase
Solution Approach 1:
The patent combines the formation of pixel electrode and transparent conductive pattern into a single photolithography process by depositing transparent conductive layer over both metal layers simultaneously. This merging of processes reduces the total number of photolithography steps from six to five, simplifying the manufacturing process while maintaining the required device performance and electrical connections.
2Ease of manufacture
If half-tone mask is used to reduce the number of photolithography processes, then the manufacturing cost is reduced, but the process control complexity and mask cost increase
Solution Approach 1:
Instead of using half-tone mask to achieve pattern formation, the patent inverts the approach by forming complete transparent conductive patterns over both metal layers in one step, then using selective etching to remove metal layers where needed. This reverses the conventional sequence of patterning first and depositing later, eliminating the need for complex half-tone masks while maintaining cost effectiveness.
3Reliability
If six photolithography processes are used for manufacturing TFT array substrate in FFS mode, then the device performance is maintained, but the manufacturing cost increases compared to TN mode
Solution Approach 1:
The patent merges the pixel electrode formation with transparent conductive pattern formation into a single photolithography process. By depositing transparent conductive layer over both metal layers simultaneously and patterning them together, the process reduces the total photolithography steps from six to five, bringing FFS mode manufacturing cost closer to TN mode while preserving the high aperture ratio and transmittance characteristics of FFS displays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for stable mass production of thin-film transistor array substrates with reduced manufacturing costs and complexity, maintaining high aperture ratios and transmittance comparable to existing FFS mode devices.
Implementation Method 1
a counter electrode that is formed on the interlayer insulating layer and generates a fringe electric field with the pixel electrode
Data Source
AI summary
A thin-film transistor array substrate includes a source line that is formed above a gate insulating layer covering a gate line, a semiconductor layer that is formed on the gate insulating layer and placed in a substantially whole area below a drain electrode, in a substantially whole area below a source electrode, in a substantially whole area below the source line and in a position opposite to the gate electrode, a pixel electrode that is formed directly on the drain electrode, a transparent conductive pattern that is formed directly on the source electrode and the source line in the same layer as the pixel electrode, and a counter electrode that is formed on an interlayer insulating layer covering the pixel electrode and the transparent conductive pattern and generates a fringe electric field with the pixel electrode.