Thin Film Transistor Array Substrate Reducing Mask Processes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of thin film transistor array substrates for organic light emitting display devices is complex and costly due to the need for multiple mask processes, leading to prolonged manufacturing time and high costs.
Innovation Solution
A thin film transistor array substrate design that includes a semiconductor active layer, gate and source/drain electrodes, insulation layers, a pixel electrode, and a protection layer, with specific material compositions and layer arrangements, allowing for a reduced number of mask processes and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to form patterns on the substrate, then the pattern transfer precision is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple mask processes into a single integrated process. Specifically, the pixel electrode layer and gate electrode layer are formed simultaneously in one mask process, and the source/drain electrodes and pad electrodes are formed in another combined mask process. This merging of previously separate mask operations into unified processes reduces the total number of masks needed while maintaining pattern precision through carefully designed electrode layer configurations.
Solution Approach 2:
The patent implements multi-functionality by designing electrode layers that serve multiple purposes. The pixel electrode layer functions both as the pixel electrode for display and as a mask for forming the gate electrode pattern. Similarly, the pad electrode pattern serves dual functions in the final structure. This multi-functional design eliminates the need for separate dedicated mask processes for each component.
2Manufacturing precision
If multiple mask processes are used to form patterns on the substrate, then the pattern transfer precision is improved, but the manufacturing time is prolonged
Solution Approach 1:
The patent merges sequential mask operations into parallel or combined processes. By forming the pixel electrode and gate electrode in a single mask step, and the source/drain and pad electrodes in another combined step, the total manufacturing time is reduced compared to performing each electrode formation as a separate mask process, while still achieving the required pattern precision.
Solution Approach 2:
The patent employs preliminary action by forming the pixel electrode layer first, which then serves as a self-aligned mask for the subsequent gate electrode formation. This preliminary structure creation eliminates the need for a separate dedicated mask for the gate electrode, streamlining the process and reducing overall manufacturing time while maintaining alignment precision.
3Manufacturing precision
If multiple mask processes are used to form patterns on the substrate, then the pattern transfer precision is improved, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple mask processes into fewer integrated processes, directly reducing the number of masks that need to be fabricated and handled. This merging approach lowers material costs (fewer masks), reduces process overhead, and decreases manufacturing complexity, thereby reducing overall production costs while preserving pattern transfer precision through the unified process design.
Solution Approach 2:
By designing electrode layers with multi-functional capabilities, the patent eliminates redundant mask processes. For example, the pixel electrode layer serves both its functional purpose and as a patterning mask, reducing the total mask count and associated costs. This universal design approach maintains manufacturing precision while significantly reducing the complexity and expense of the manufacturing process.
Data Source
AI summary
A thin film transistor array substrate may include a thin film transistor including an active layer, a gate electrode, source and drain electrodes, a first insulation layer arranged between the active layer and the gate electrode, and a second insulation layer arranged between the gate electrode and the source and drain electrodes, a pixel electrode arranged on the first insulation layer and comprising the same material as the gate electrode, a capacitor comprising a first electrode arranged on the same layer as the active layer and a second electrode arranged on the same layer as the gate electrode, a pad electrode arranged on the second insulation layer and comprising the same material as the source and drain electrodes, a protection layer formed on the pad electrode, and a third insulation layer formed on the protection layer and exposing the pixel electrode.