TFT Array Substrate with n- a-Si Layer for LCD Fabrication
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Solution Overview
Problem
The existing methods for fabricating liquid crystal display (LCD) array substrates require multiple photolithography processes, leading to reduced production yield and poor electrical characteristics of thin film transistors due to high resistance between the channel layer and ohmic-contact layer, as well as uncontrolled threshold voltage.
Innovation Solution
The introduction of a thin film transistor structure with a gate electrode, source and drain electrodes, and an active region featuring a first and second semiconductor layer with an ohmic contact layer, where the n− amorphous silicon layer is formed between the active layers to reduce serial resistance and improve conductivity, allowing for single masking processes and controlled threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple photolithography processes are used to fabricate the array substrate, then the TFT structure can be formed, but the production yield decreases and manufacturing complexity increases
Solution Approach 1:
The patent combines multiple photolithography processes into a single masking process by designing the mask pattern to simultaneously define the active layer, source/drain electrodes, and contact holes. This merging of processes reduces manufacturing steps, increases production yield, and maintains TFT electrical characteristics by ensuring precise alignment in one step.
Solution Approach 2:
The single mask pattern serves multiple functions by simultaneously defining the active layer boundaries, source and drain electrode positions, and contact hole locations. This multi-functional mask design eliminates the need for separate photolithography processes while maintaining the required structural precision for TFT fabrication.
2Reliability
If multiple photolithography processes are used, then the TFT structure can be formed, but the device complexity increases
Solution Approach 1:
The patent merges multiple photolithography processes into a single masking operation, reducing fabrication process complexity. The single mask pattern is designed to simultaneously define all critical features (active layer, electrodes, contact holes), eliminating sequential processing steps and reducing overall device fabrication complexity.
3Ease of manufacture
If the channel layer and ohmic-contact layer are formed with high resistance, then the fabrication is simpler, but the ON-current and charge mobility deteriorate
Solution Approach 1:
The patent applies local quality by forming an n-type doped amorphous silicon layer specifically in the contact region between the channel layer and ohmic-contact layer. This localized doping reduces resistance at the critical interface without complicating the overall fabrication process, thereby improving ON-current and charge mobility while maintaining ease of manufacture.
4Ease of manufacture
If the threshold voltage is uncontrolled, then the fabrication process is simpler, but the electrical characteristics deteriorate
Solution Approach 1:
The patent controls threshold voltage by adjusting the doping concentration and thickness of the n-type amorphous silicon layer in the contact region. By changing these physical parameters, the threshold voltage is precisely controlled without adding complex fabrication steps, maintaining ease of manufacture while improving electrical characteristics.
Data Source
AI summary
A thin film transistor (TFT) for a liquid crystal display device includes a gate electrode, a source electrode, a drain electrode, an active region including a first semiconductor layer and a second semiconductor layer interposed within the first semiconductor layer, and an ohmic contact layer formed on the active region, wherein the source and drain electrodes are formed on the ohmic contact layer.