Thin Film Transistor Array Substrate with Multi-Layer Active Layer Overlap
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Solution Overview
Problem
Current thin film transistor array substrates lack novel designs, with inefficient wiring and suboptimal reliability and display quality, particularly due to excessive parasitic capacitance causing pixel voltage errors and twinkling issues.
Innovation Solution
A thin film transistor array substrate design featuring an active layer with overlapping sections, such as a 'U' shape, where the active layer and signal lines overlap at multiple positions, reducing parasitic capacitance by strategically positioning signal lines and active layers to minimize capacitance between data lines and channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the active layer and signal line are positioned in conventional single-layer configurations, then the manufacturing process is simple, but parasitic capacitance is excessive causing pixel voltage errors and twinkling
Solution Approach 1:
The patent transitions from conventional single-layer planar configuration to multi-layer three-dimensional configuration. The active layer is positioned in a first layer while the signal line is positioned in a second layer, creating vertical separation that reduces parasitic capacitance. This dimensional change resolves the contradiction by reducing harmful electrical interference while maintaining manufacturing feasibility through standard multi-layer TFT fabrication processes.
2Reliability
If the active layer overlaps with the signal line at multiple positions, then parasitic capacitance is reduced, but wiring complexity increases
Solution Approach 1:
The patent uses vertical layering to achieve multiple overlap positions between the active layer and signal line without increasing horizontal wiring complexity. By positioning the active layer and signal line in different layers (first layer and second layer respectively), the design achieves multi-position overlap in the vertical dimension, reducing parasitic capacitance while maintaining simple planar wiring patterns.
Solution Approach 2:
The patent implements nesting by placing the signal line within the vertical projection area of the active layer. The signal line is positioned to overlap with the active layer at multiple positions when viewed from the top, creating a nested configuration where the signal line is effectively 'nested' within the active layer's footprint, maximizing overlap for capacitance reduction without extending wiring boundaries.
3Reliability
If conventional single-layer structure is used, then device structure is simple, but wiring efficiency and reliability are insufficient
Solution Approach 1:
The patent employs multi-layer configuration where the active layer and signal line are positioned in different vertical layers. This vertical separation reduces parasitic capacitance between the active layer and signal line, improving thin film transistor reliability and reducing display defects such as pixel voltage errors and twinkling, while the overall device structure remains compatible with standard multi-layer TFT manufacturing processes.
Data Source
Figure 1A~1C
Figure 2
Figure 3~4
AI summary
The present disclosure provides a thin film transistor array substrate and a display device implementing the same. The thin film transistor array substrate includes a substrate; a first signal line formed on the substrate; and a thin film transistor formed on the substrate, and an active layer of the thin film transistor and the first signal line are located on different layers above the substrate and projections of them on a plane where the substrate is located overlap with each other at at least two positions. The present disclosure may improve wiring efficiency and reliability of the thin film transistor array substrate.