TFT Array Substrate with Dual-Layer Insulator for Parasitic Capacitance Reduction
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Solution Overview
Problem
Existing organic light-emitting display apparatuses face challenges in reducing parasitic capacitance and signal interference due to overlapping wires and transistors, which affect storage capacitance and display quality.
Innovation Solution
A thin-film transistor array substrate is designed with a specific structure, including a second interlayer insulating film with a higher thickness and lower dielectric constant than the first interlayer insulating film, and made of organic material, which reduces parasitic capacitance by blocking interference between wires and transistors, while maintaining high storage capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If wires and transistors are arranged in overlapping configurations to increase integration density, then device complexity is reduced and area is minimized, but parasitic capacitance increases and signal interference occurs
Solution Approach 1:
A dual-layer insulating film structure is introduced as an intermediary between overlapping conductive layers. The first insulating film layer and second insulating film layer work together to electrically isolate wires and transistors that overlap in the planar view, thereby reducing parasitic capacitance and signal interference while maintaining high integration density
Solution Approach 2:
The insulating film is constructed as a composite structure with two distinct layers having different dielectric properties. This composite approach allows optimization of each layer's thickness and material characteristics to achieve minimal parasitic capacitance while providing sufficient electrical isolation for the overlapping conductor configuration
2Reliability
If storage capacitor size is increased to improve image holding capability, then storage capacitance increases, but device area increases and integration density decreases
Solution Approach 1:
The storage capacitor utilizes the vertical dimension by forming the second insulating film layer above the first insulating film layer. This three-dimensional arrangement allows the capacitor to achieve sufficient storage capacitance through increased effective area in the vertical direction without proportionally increasing the planar footprint, thereby maintaining high integration density while improving image holding capability
Data Source
AI summary
A thin-film transistor (TFT) array substrate includes a driving TFT, a storage capacitor, a first wire, a first interlayer insulating film, a second interlayer insulating film, and a second wire. The storage capacitor has a first electrode connected to a driving gate electrode of the driving TFT and a second electrode on and insulated from the first electrode. The first wire is on a same layer as the driving gate electrode. The first interlayer insulating film covers the first electrode and the first wire. The second interlayer insulating film is on the first interlayer insulating film and includes an opening that exposes part of the first interlayer insulating film. The second wire is on the second interlayer insulating film and at least partially overlaps the first wire. The second electrode is in the opening of the second interlayer insulating film.