TFT Array Substrate Patterning Process Optimization
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Solution Overview
Problem
The conventional manufacturing method of TFT array substrates requires six photolithographic processes, which increases production time and costs, limiting efficiency and scalability.
Innovation Solution
A method that reduces the number of patterning processes to four by combining certain layers and using gray-tone or half-tone masks to form metal oxide semiconductor layers and etching barrier layers in one process, and source, drain, and pixel electrodes in another, simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If six photolithographic processes are used to manufacture TFT array substrate, then manufacturing precision and reliability are improved, but productivity is reduced and manufacturing cost increases
Solution Approach 1:
The patent combines two separate photolithographic processes into one by using a dual-layer photoresist structure. The first photoresist layer patterns the metal oxide semiconductor layer, while the second photoresist layer patterns the electrode layers. This merging reduces the total number of photolithographic processes from six to four, thereby improving productivity while maintaining manufacturing precision through the layered approach.
2Reliability
If six photolithographic processes are used to manufacture TFT array substrate, then TFT structure reliability is improved, but manufacturing cost increases
Solution Approach 1:
By merging photolithographic processes and using a dual-layer photoresist system, the patent reduces the number of masks and processing steps required. This decreases material costs and manufacturing complexity while maintaining TFT reliability through controlled patterning of semiconductor and electrode layers in sequence.
Solution Approach 2:
The photoresist layers serve multiple functions: they act as patterning masks for different layers, provide structural support during processing, and enable sequential deposition of multiple functional layers (semiconductor, electrode, insulator) in an organized manner, reducing the need for separate specialized processes.
3Manufacturing precision
If six photolithographic processes are used, then complete layer patterning is achieved, but production time increases
Solution Approach 1:
The patent merges multiple patterning operations into fewer photolithographic cycles by using stacked photoresist layers. Each photoresist layer is deposited, patterned, and used as a mask for subsequent deposition steps, allowing multiple layers to be patterned in parallel sequences rather than requiring six separate sequential photolithographic processes, thus reducing production time.
Solution Approach 2:
The first photoresist layer is deposited and patterned in advance to define the metal oxide semiconductor layer pattern. This preliminary patterning establishes a template for subsequent electrode layer deposition, allowing the second photoresist layer to be applied and patterned more efficiently without repeating the full photolithographic sequence for each layer.
Data Source
AI summary
A manufacturing method of a TFT array substrate is provided. The method includes the following steps: respectively forming a metal oxide semiconductor layer, an etching barrier layer, a source electrode, a data line, a drain electrode, a pixel electrode, a gate insulating layer, a contact hole, a gate electrode and a gate scanning line on a substrate by patterning processes, wherein the metal oxide semiconductor layer and the etching barrier layer are formed by a same patterning process, and the source electrode, the drain electrode, the pixel electrode and the data line are formed by another same patterning process.