TFT Array Substrate with Shared Gate and Capacitor Electrodes
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Solution Overview
Problem
The manufacturing process of flat panel display devices, such as organic light emitting display devices, is complex and costly due to the need for multiple mask processes and the preparation of masks with fine patterns, which increases the time and expense of producing thin film transistors and capacitors.
Innovation Solution
A thin film transistor array substrate is designed with a semiconductor active layer, gate and drain electrodes, a capacitor with shared electrodes, and insulation layers, along with a protection layer to prevent pinhole defects and leakage currents, using a method that reduces the number of mask processes and simplifies the manufacturing by doping ion impurities into the semiconductor material and forming the electrodes and wiring in the same layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used to form fine patterns of TFT and capacitor, then manufacturing precision is improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent combines the formation of TFT and capacitor patterns into a single mask process. The gate electrode and capacitor electrodes are formed simultaneously using one mask, eliminating the need for separate masking steps. This merging approach maintains manufacturing precision while reducing process complexity and manufacturing time.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it defines both the TFT gate electrode pattern and the capacitor electrode pattern simultaneously. This multi-functional mask design eliminates the need for multiple specialized masks, reducing device complexity in the manufacturing process while maintaining the required fine pattern precision.
2Manufacturing precision
If multiple mask processes are used to form fine patterns, then manufacturing precision is improved, but manufacturing time increases
Solution Approach 1:
The patent merges multiple patterning operations into a single mask process. By forming both TFT and capacitor patterns simultaneously using one mask, the manufacturing time is reduced while maintaining fine pattern precision. This eliminates sequential mask application steps and associated time losses.
Solution Approach 2:
The single mask is designed in advance to contain all necessary pattern definitions for both TFT and capacitor structures. This preliminary design approach allows all fine patterns to be formed in one exposure and development cycle, reducing manufacturing time while preserving the precision that would otherwise require multiple iterative mask processes.
3Manufacturing precision
If multiple mask processes are used, then manufacturing precision is improved, but manufacturing costs increase
Solution Approach 1:
The patent combines multiple mask-making and mask-application processes into a single operation. This merging eliminates the need to manufacture multiple expensive fine-pattern masks, reducing material costs and process costs while maintaining the required manufacturing precision through the unified mask design.
Solution Approach 2:
The single mask performs multiple patterning functions that would otherwise require separate masks. This multi-functionality reduces the total number of masks needed, lowering manufacturing costs associated with mask fabrication, storage, and handling, while maintaining fine pattern precision through careful mask design.
4Area of stationary object
If insulation layers are formed close to capacitor electrodes, then area is reduced, but pinhole defects and leakage currents increase
Solution Approach 1:
The patent applies different insulation layer configurations at different locations. The first insulation layer is formed between the gate electrode and active layer, while the second insulation layer is formed between the capacitor electrodes. This local differentiation allows the insulation layers to be positioned closely to reduce area while maintaining electrical reliability through appropriate insulation material selection and layer positioning.
Solution Approach 2:
The patent introduces a protective layer as an intermediary between the insulation layers and the capacitor electrodes. This protective layer prevents pinhole defects and leakage currents by providing an additional barrier, allowing the insulation layers to be positioned closely for area reduction while maintaining electrical reliability through the intermediary protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrostatic capacity, improves signal transmission quality, and reduces manufacturing complexity and costs by minimizing the need for multiple mask processes and preventing pinhole defects and leakage currents.
Implementation Method 1
doping ion impurities into the semiconductor material
Data Source
AI summary
A thin film transistor array substrate includes a thin film transistor on a substrate, the thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; a capacitor including a lower electrode in a same layer as the active layer and an upper electrode in a same layer as the gate electrode; a pixel electrode in a same layer as the gate electrode and the upper electrode; a first insulation layer between the active layer and the gate electrode and between the lower electrode and the upper electrode; a second insulation layer on the first insulation layer, a protection layer extending along side surfaces of the lower electrode, and a third insulation layer on the protection layer and exposing the pixel electrode.