TFT Array Substrate Single Patterning Process
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Solution Overview
Problem
The existing method for manufacturing TFT array substrates with advanced super dimension switch (ADS) display mode is complex and costly due to its intricate patterning process.
Innovation Solution
A simplified method involving four patterning processes to manufacture a top-gate TFT array substrate, using copper-based metals for the electrodes, and employing a single patterning process for forming key layers and electrodes, with specific etching and photoresist application steps to reduce complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional multi-step patterning process is used to manufacture TFT array substrate with ADS display mode, then the manufacturing precision and electrode pattern accuracy are improved, but the device complexity and production cost increase significantly
Solution Approach 1:
The patent combines multiple patterning operations into a single exposure step using a specific mask plate design. The mask plate includes transparent regions, opaque regions, and semi-transparent regions that enable simultaneous formation of common electrode, common electrode line, gate line, and data line patterns in one exposure process, thereby reducing process complexity while maintaining pattern accuracy
Solution Approach 2:
The mask plate serves multiple functions simultaneously: it defines boundaries for different electrode types, controls material deposition areas, and creates both transparent and opaque regions in a single component. This multi-functional mask plate eliminates the need for multiple specialized mask plates and exposure steps
2Device complexity
If a simplified single patterning process is used to manufacture TFT array substrate, then the device complexity and production cost are reduced, but the manufacturing precision and electrode pattern accuracy may deteriorate
Solution Approach 1:
The mask plate employs different optical properties in different regions: fully transparent regions allow complete light transmission for certain patterns, fully opaque regions block light for other patterns, and semi-transparent regions provide partial transmission for intermediate patterns. This local variation in optical quality enables precise control over electrode formation in different areas during a single exposure process
Solution Approach 2:
The invention changes the optical transmission parameter of the mask plate across different regions to achieve different patterning outcomes simultaneously. By adjusting the transparency parameter from 0% (opaque) to 50% (semi-transparent) to 100% (transparent), the system can create multiple electrode patterns with different characteristics in one exposure step without sacrificing precision
3Reliability
If conventional manufacturing methods are used, then the electrode connections are reliable, but the production cost and manufacturing time increase
Solution Approach 1:
The single patterning process performs all necessary electrode pattern definitions in advance during one exposure step. The mask plate pre-establishes the spatial relationships and connection points between common electrode, common electrode line, gate line, and data line, ensuring reliable connections are built into the design from the outset rather than requiring multiple verification steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces production costs, and enhances the yield and performance of the TFT array substrate by minimizing defects and copper diffusion effects.
Implementation Method 1
applying a photoresist onto the first metal film; exposing and developing the photoresist with a gray-tone or half-hone mask plate, so as to form a photoresist reserved region corresponding to a region where the patterns of the common electrode line, the gate line and the data line are located
Implementation Method 2
etching off the first metal film and the first transparent conductive film at the photoresist unreserved region by an etching process
Data Source
AI summary
The present disclosure provides a thin film transistor (TFT) array substrate, its manufacturing method and a display device. The method includes steps of: forming patterns of a common electrode, a common electrode line, a gate line and a data line on a substrate by a single patterning process; forming an insulating layer; forming a pattern of an active layer by a single patterning process; forming a gate insulating layer and forming via-holes corresponding to the gate line, the data line and the active layer in the gate insulating layer by a single patterning process; and forming patterns of a pixel electrode, a gate electrode, a source electrode and a drain electrode by a single patterning process.