Thin-Film Transistor Array Substrate Via Hole Reliability
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Solution Overview
Problem
The existing design of OLED displays faces challenges in improving Pixels Per Inch (PPI) and stability due to the need for large source-drain electrode metal areas to prevent etching of gate electrode metal, which complicates wiring interconnections and increases via hole resistance.
Innovation Solution
Incorporating an oxide semiconductor layer as an etch stop layer, allowing for reduced source-drain electrode metal area and improved exposure precision by using different photomasks for the semiconductor and metal layers, enabling closer wiring proximity to via holes and reducing the risk of gate electrode metal etching during dry etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source-drain electrode metal area is increased to prevent etching of gate electrode metal, then the reliability of via hole connection is improved, but the device complexity and wiring design difficulty increase
Solution Approach 1:
The patent introduces an intermediate protective layer between the source-drain electrode metal and the gate electrode metal. This intermediate layer acts as a mediator that prevents direct etching of the gate electrode metal while allowing the source-drain electrode metal to maintain a smaller, more manageable area. The intermediate layer is selectively removed in via hole regions to establish connections while protecting gate electrode metal in other areas.
Solution Approach 2:
The patent segments the protective function by introducing a separate intermediate layer that is distinct from both the source-drain electrode metal and the gate electrode metal. This segmentation allows the source-drain electrode metal to be smaller while still providing protection where needed, as the intermediate layer handles the protective function independently.
2Reliability
If the source-drain electrode metal area is increased to ensure complete via hole coverage, then the risk of gate electrode metal etching is reduced, but the Pixels Per Inch (PPI) and exposure precision deteriorate
Solution Approach 1:
The intermediate layer serves as a mediator that enables precise via hole formation without requiring large source-drain electrode metal areas. The via holes are formed through the intermediate layer, which provides a clear etching target and stop layer, improving exposure precision while maintaining via hole coverage reliability.
Solution Approach 2:
The patent adds a vertical dimension to the protective structure by introducing an intermediate layer at a different vertical level between the source-drain electrode metal and the gate electrode metal. This dimensional separation allows for precise via hole positioning and formation without requiring excessive horizontal overlap of the source-drain electrode metal.
3Reliability
If the source-drain electrode metal area is increased to prevent gate electrode metal exposure, then the via hole erosion risk is reduced, but the manufacturing precision and wiring design flexibility worsen
Solution Approach 1:
The intermediate layer acts as a dedicated etching stop layer that defines the via hole boundaries with high precision. Etching stops at the intermediate layer, preventing over-etching and ensuring accurate via hole formation. This intermediary structure provides a clear etching target that improves manufacturing precision while maintaining via hole stability.
Solution Approach 2:
The intermediate layer is formed in advance before via hole etching, establishing a predefined etching stop boundary. This preliminary action ensures that subsequent etching processes will automatically stop at the correct location, improving via hole formation precision and reducing the need for large source-drain electrode metal areas for alignment margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances design flexibility and reduces via hole resistance, allowing for improved PPI and stability in OLED displays by preventing unnecessary etching of the gate electrode metal and allowing for more precise wiring arrangements.
Implementation Method 1
Incorporating an oxide semiconductor layer as an etch stop layer, allowing for reduced source-drain electrode metal area and improved exposure precision by using different photomasks for the semiconductor and metal layers, enabling closer wiring proximity to via holes and reducing the risk of gate electrode metal etching during dry etching.
Data Source
AI summary
A thin-film transistor array substrate is disclosed. The array substrate includes a support substrate, a plurality of scan lines on the support substrate, and a plurality of data lines on the support substrate, where the plurality of scan lines are insulated and intersect with the plurality of data lines. The array substrate also includes a plurality of pixel units located near intersections of the scan lines and the data lines, a first metal layer on the support substrate, and an insulating layer on the first metal layer, where the insulating layer includes a plurality of via holes, each exposing a portion of the first metal layer. The array substrate also includes a semiconductor layer on the insulating layer and electrically connected to the first metal layer, and a second metal layer on the semiconductor layer and electrically connected to the semiconductor layer.