TFT Array Substrate Three-Patterning Yield Improvement
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Solution Overview
Problem
The three-patterning process for manufacturing TFT array substrates has a relatively low yield due to the photoresist stripping-off technology used in the prior art, limiting its application in production.
Innovation Solution
A method involving a first patterning process to form an active layer with separated source and drain electrodes, a second patterning process to create a contact via hole in an insulating layer exposing the source electrode, and a third patterning process to form a pixel electrode connected to the source electrode through the via hole, reducing the number of patterning processes and increasing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the three-patterning process is used to manufacture TFT array substrates, then the manufacturing time and cost are reduced, but the yield is relatively low due to photoresist stripping-off technology
Solution Approach 1:
The patent extracts and removes the photoresist stripping-off process from the manufacturing flow by using a novel patterning approach where photoresist is not stripped off, thereby eliminating the source of low yield while maintaining the benefits of reduced patterning steps
Solution Approach 2:
Instead of following the conventional approach of forming patterns and then stripping photoresist, the patent inverts the sequence by maintaining photoresist patterns through additional patterning steps, allowing the photoresist to serve as a permanent mask rather than a temporary one
2Reliability
If the four-patterning process is used, then the yield is improved, but the manufacturing time and cost increase
Solution Approach 1:
The patent merges multiple patterning operations into a unified three-step process where the photoresist patterns are reused across different metal layer formations, eliminating redundant steps while maintaining high yield through careful process integration
3Productivity
If the number of patterning processes is reduced, then the production efficiency is improved, but the manufacturing precision may deteriorate
Solution Approach 1:
The patent performs preliminary patterning of the photoresist layer with precise geometric definitions before subsequent metal depositions, ensuring that all critical dimensions are established in advance when the photoresist mask is most stable and accurate
Data Source
AI summary
Embodiments of the present invention disclose a thin film transistor array substrate and a method for manufacturing the same and an electronic device. The method for manufacturing the thin film transistor array substrate comprises: a first patterning process, in which a pattern of an active layer which is formed by a semiconductor layer and patterns of a source electrode and a drain electrode, which are separated from each other and are formed by a first metal layer, are formed on a transparent substrate; a second patterning process, in which a pattern of an insulating layer is formed on the transparent substrate subjected to the first patterning process, the pattern of the insulating layer comprising a contact via hole exposing the source electrode; and a third patterning process, in which a pattern of a pixel electrode, which is formed by a transparent conductive layer, and a pattern of a gate electrode, which is formed by a second metal layer, are formed on the transparent substrate subjected to the second patterning process, the pixel electrode being connected to the source electrode through the contact via hole.