TFT Backplane Gate Insulating Layer Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reliability of low temperature poly silicon (LTPS) thin film transistor (TFT) backplanes in AMOLED displays is compromised due to the poor interface stress between the SiNx layer and the polysilicon active layer, leading to reduced reliability and performance, especially in the storage capacitor area, which also increases the capacitor area and reduces the aperture ratio.
Innovation Solution
A TFT backplane structure with a three-layered gate insulating layer comprising a dielectric layer, a SiNx layer, and a SiO2 layer at the TFT location, and a two-layered or single-layered structure at the storage capacitor location, using a lithography etching process to optimize the layer thickness and prevent carrier injection and excessive etching, thereby enhancing reliability and reducing capacitor area while maintaining storage capacitance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a SiO2 layer is deposited plus a layer of SiNx layer to form the gate insulating layer, then the interface quality between SiNx layer and polysilicon active layer is improved, but the thickness of the gate insulating layer corresponding to storage capacitor area is increased
Solution Approach 1:
The patent applies different gate insulating layer structures to different functional areas: the TFT area uses a three-layered structure (dielectric layer + SiNx layer + SiO2 layer) for high interface quality, while the storage capacitor area uses a two-layered structure (dielectric layer + SiNx layer) or single-layered structure (dielectric layer only) to reduce thickness. This local differentiation resolves the contradiction by optimizing each area for its specific function.
Solution Approach 2:
The gate insulating layer is segmented into different thickness configurations across different regions of the substrate. The TFT region receives the full three-layered structure for reliability, while the storage capacitor region receives a reduced structure for performance optimization. This segmentation allows simultaneous achievement of both interface quality and reduced capacitor area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure improves TFT reliability, reduces capacitor area, and enhances aperture ratio by preventing carrier injection and excessive etching, ensuring stable performance and efficient capacitance storage.
Implementation Method 1
the SiO2 layer prevents the gate from injecting carriers to the SiNx layer to avoid damage
Implementation Method 2
using a lithography etching process to etch the gate insulating layer at a location corresponding to forming a storage capacitor to rid of the entire SiO2 layer and a portion of the SiNx layer at the location
Implementation Method 3
the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area
Data Source
AI summary
The invention provides a TFT backplane structure and manufacturing method thereof. The TFT backplane structure uses the three-layered structure, from bottom up, dielectric layer (41), SiNx layer (42), and SiO2 layer (43), for the gate insulating layer (4) corresponding to the location of the TFT (T), to enhance the TFT reliability; uses a double-layered gate insulating layer (4), from bottom up, the dielectric layer (41), and at least a portion of SiNx layer (42), at the location corresponding to the storage capacitor (C), or a single-layered gate insulating layer (4), i.e., the dielectric layer (4), at the location corresponding to the storage capacitor (C), the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area and improve aperture ratio on the premise of storage capacitance performance.