TFT Backplane Manufacturing via Half-Tone Mask Polysilicon Patterning
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Solution Overview
Problem
The traditional manufacturing method of TFT backplanes using solid-phase crystallization (SPC) requires multiple masks and two ion implantations, increasing production costs due to complex processes and high mask requirements.
Innovation Solution
A manufacturing method utilizing a half-tone mask to pattern the polysilicon layer, forming an island active layer with implanted ions, where the upper layer portion is etched to create a channel region and the sides form source/drain contact regions, reducing the number of masks and eliminating the need for additional ion implantation steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional SPC manufacturing method with multiple masks and ion implantations is used, then the TFT backplane can be manufactured with pure polysilicon semiconductor layer, but the production cost increases and process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-implanting induced ions into the amorphous silicon layer before crystallization. This preliminary ion implantation creates a polysilicon layer with non-uniform ion distribution, where the upper layer has more implanted ions and the lower layer has purer polysilicon. This preliminary preparation eliminates the need for subsequent ion implantation steps and multiple masking processes, directly resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent segments the polysilicon layer into two distinct regions: an upper layer portion with more implanted induced ions and a lower layer portion with purer polysilicon. By patterning only the upper layer portion, the method selectively removes the ion-rich region while retaining the pure polysilicon region for the semiconductor layer. This segmentation approach maintains manufacturing precision while simplifying the overall process by combining multiple functions into a single patterning step.
2Reliability
If multiple masks and ion implantations are used in traditional SPC method, then the TFT backplane structure can be formed, but the production cost increases
Solution Approach 1:
The patent merges multiple separate manufacturing steps into a single integrated process. The method combines the formation of the polysilicon layer, the creation of the upper layer portion with implanted ions, and the patterning into one continuous process flow. By using a half-tone mask to directly pattern the polysilicon layer after crystallization, the patent eliminates the need for separate ion implantation steps and multiple masking operations, thereby maintaining structural reliability while significantly reducing production cost.
Solution Approach 2:
The patent applies self-service by utilizing the inherent non-uniform ion distribution within the polysilicon layer itself. The upper layer portion naturally contains more implanted ions due to the crystallization process, and this self-formed structure is directly utilized for patterning. The method eliminates the need for external ion implantation equipment and multiple mask alignment processes, allowing the material structure to serve its own patterning function and reducing manufacturing cost.
3Manufacturing precision
If traditional method with separate patterning and ion implantation steps is used, then the source/drain contact region can be formed, but the number of masks increases
Solution Approach 1:
The patent applies universality by making the polysilicon layer patterned structure serve multiple functions simultaneously. The half-tone mask patterning process not only defines the active layer geometry but also directly creates the source/drain contact regions by exposing the underlying structure in specific areas. This single patterning step performs what traditionally required separate masking and ion implantation steps, reducing the quantity of masks needed while maintaining manufacturing precision for source/drain contact region formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the process and lowers production costs by reducing the number of masks and eliminating unnecessary ion implantation steps, resulting in a more efficient and cost-effective TFT backplane production.
Implementation Method 1
implanting an induced ion into the amorphous silicon (a-Si) layer 300 and performing a high-temperature baking, such that the amorphous silicon performs the crystallization rapidly to generate the polysilicon layer 300'
Implementation Method 2
implanting an induced ion into the amorphous silicon (a-Si) layer 300
Data Source
AI summary
The disclosure provides a manufacturing method and a structure thereof of a TFT backplane. In the manufacturing method of the TFT backplane, after a polysilicon layer (3′) is formed by implanting a induced ion solid-phase crystallization into an amorphous silicon layer (3), patterning the polysilicon layer using a half-tone mask to form an island active layer (4), and at the same time, etching a upper layer portion (31) with more implanted induced ions located in the middle portion of the island active layer (4) to form a channel region, retaining the upper layer portion (31) with more implanted induced ions located in two sides of the island active layer (4) to form a source/drain contact region, it not only reduces the number of masks, but also saves a process only for implanting doped ion into the source/drain contact region, thereby simplifying the process and reducing production cost.