TFT Backplane Leakage Current Reduction via High Bandgap Semiconductors
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Solution Overview
Problem
Display panels in portable electronics face significant power consumption challenges due to high refresh rates, which can lead to flicker when reduced, primarily caused by leakage current in Thin Film Transistor (TFT) backplanes.
Innovation Solution
Fabricating TFT backplanes with reduced leakage current using high bandgap materials like indium phosphide or gallium phosphide, allowing for lower refresh rates without causing flicker, achieved through semiconductor fabrication techniques such as the Vapor-Liquid-Solid process and doping to form n-type or p-type semiconductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the refresh rate is reduced to save power, then power consumption is reduced, but flicker occurs due to leakage current
Solution Approach 1:
The patent changes the material parameter (bandgap) of the semiconductor layer from conventional materials to high bandgap materials like indium phosphide or gallium phosphide. This material parameter change reduces the leakage current, enabling the refresh rate to be lowered without causing flicker, thus resolving the contradiction between power consumption and flicker prevention.
Solution Approach 2:
The patent employs composite material structures including the semiconductor layer, buffer layer, and various electrode layers. The specific combination of high bandgap semiconductor materials with appropriate buffer and electrode materials creates a structure that minimizes leakage current while maintaining display performance, allowing reduced refresh rates without flicker.
2Ease of manufacture
If traditional materials like amorphous silicon or IGZO are used, then manufacturing is easier, but leakage current is high causing flicker at low refresh rates
Solution Approach 1:
The patent changes the key material parameter (bandgap) from conventional semiconductor materials to high bandgap materials. This parameter change fundamentally reduces leakage current, enabling operation at lower refresh rates without flicker, while maintaining compatibility with existing thin-film transistor fabrication processes.
3Use of energy by moving object
If high bandgap materials are used, then leakage current is reduced enabling lower refresh rates, but manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameter (bandgap) to high bandgap materials, which reduces leakage current and enables lower refresh rates. The manufacturing complexity increase is managed by using thin-film deposition techniques that are compatible with existing display fabrication processes.
Solution Approach 2:
The patent introduces a buffer layer as an intermediary between the substrate and the high bandgap semiconductor layer. This buffer layer facilitates the growth of high quality semiconductor films and manages stress, simplifying the overall manufacturing process despite using advanced materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables display panels to operate at lower refresh rates, reducing power consumption while preventing flicker, and improving reliability and stability compared to traditional materials like amorphous silicon or IGZO.
Implementation Method 1
achieved through semiconductor fabrication techniques such as the Vapor-Liquid-Solid process
Implementation Method 2
doping to form n-type or p-type semiconductors
Data Source
AI summary
A display panel with reduced power consumption is described. An example of the display panel includes an array of light emitting elements that are controllable to form an image, and a Thin-Film-Transistor (TFT) backplane comprising circuitry to drive the array of light emitting elements. The TFT backplane includes a plurality of field effect transistors (FETs). Each FET includes a source electrode, a drain electrode, a channel layer contacting the source electrode and the drain electrode, and a gate electrode adjacent to the channel layer and separated from the channel layer by an insulator. The channel layer includes a layer of metal phosphide.


