Multi-Blocking-Layer TFT Layout to Reduce Display Crosstalk
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Solution Overview
Problem
Display apparatuses face issues with crosstalk due to parasitic capacitance between the blocking layer and data line, which occurs when a metal blocking layer is used as an additional gate electrode, leading to increased operation current and reduced efficiency.
Innovation Solution
A display apparatus design featuring multiple blocking layers with varying sizes and configurations, including a second blocking layer with a larger lower surface area than the first, and buffer layers strategically positioned to prevent direct contact and minimize parasitic capacitance, allowing for a double gate electrode structure without the need for contact holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a metal blocking layer is used as an additional gate electrode to prevent leakage current, then light blocking capability is improved, but parasitic capacitance increases causing crosstalk
Solution Approach 1:
The blocking layer is divided into multiple segments (first blocking layer 210, second blocking layer 220, third blocking layer 230) with different sizes and positions. The first blocking layer has a smaller area, the second blocking layer has a larger area, and the third blocking layer has a moderate area. This segmentation allows each layer to contribute to light blocking while minimizing the total parasitic capacitance by reducing the overlapping area with the data line.
2Stability of the object's composition
If an insulation layer is added to cover the blocking layer and data line to prevent contact defects, then substrate flatness is improved, but device complexity increases
Solution Approach 1:
The insulation function is merged into the buffer layers (first buffer layer 310 and second buffer layer 320) that are already part of the TFT structure. These buffer layers serve dual purposes: providing electrical insulation between conductive elements and maintaining substrate flatness, thereby eliminating the need for a separate dedicated insulation layer.
3Object-generated harmful factors
If buffer layers are positioned apart from blocking layers to minimize parasitic capacitance, then crosstalk is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The buffer layers and blocking layers are positioned asymmetrically rather than directly overlapping. The first buffer layer is positioned apart from the first blocking layer, the second buffer layer is positioned apart from the second blocking layer, and the third blocking layer is positioned between the buffer layer and data line. This asymmetric arrangement minimizes parasitic capacitance while maintaining manufacturability.
Data Source
AI summary
A display apparatus can include a first blocking layer provided on a substrate, a second blocking layer provided on the first blocking layer, a first buffer layer provided on the second blocking layer, a third blocking layer provided on the first buffer layer, a second buffer layer provided on the third blocking layer, and a thin film transistor (TFT) provided on the second buffer layer to overlap the first to third blocking layers. Further, a size of a lower surface of the second blocking layer can be greater than a size of an upper surface of the first blocking layer.