Thin Film Transistor Buffer Layer Overlap Capacitance
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Solution Overview
Problem
In manufacturing high-resolution large-area displays using thin film transistors with a bottom-gate structure, reducing transistor sizes while maintaining on-current characteristics is challenging due to increased overlap capacitance, which can damage electrodes and require thicker gate insulating layers.
Innovation Solution
A thin film transistor design featuring a buffer layer covering side portions of the gate electrode, a thinly formed gate insulating layer, and etching stop layers with openings for source and drain electrodes, allowing for reduced transistor size without increasing overlap capacitance, along with a storage capacitor design using a similar structure to enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the thickness of the gate insulating layer is decreased to reduce transistor size, then the transistor size is reduced, but the overlap capacitance increases and electrode damage risk increases
Solution Approach 1:
The patent applies local quality by forming a buffer layer with different material composition and thickness characteristics at specific locations. The buffer layer is formed to have a first thickness in the overlap region and a second thickness in the non-overlap region, creating localized structural variations that protect electrodes in critical areas while maintaining overall transistor miniaturization
Solution Approach 2:
The patent introduces a vertical dimension solution by creating a multi-layer structure with the buffer layer positioned between the gate insulating layer and the active layer. This vertical stratification allows the gate insulating layer to be thin overall while the buffer layer provides localized thickness variation to protect against electrode damage in the overlap region
2Reliability
If the thickness of the gate insulating layer is increased to prevent overlap capacitance increase, then the overlap capacitance is reduced, but the transistor size increases
Solution Approach 1:
The buffer layer is configured with different thicknesses in different regions: a first thickness in the overlap region to control capacitance, and a second thickness in the non-overlap region. This localized differentiation allows capacitance control where needed while minimizing overall transistor size
Solution Approach 2:
The gate insulating layer structure is segmented into multiple functional layers: the gate insulating layer and the buffer layer with distinct thickness characteristics. This segmentation allows independent optimization of each layer's thickness for its specific function, enabling overall transistor size reduction while maintaining capacitance control
3Area of moving object
If the transistor size is reduced to secure opening ratio, then the opening ratio is improved, but the on-current characteristics deteriorate
Solution Approach 1:
The buffer layer provides localized structural support and electrical property modulation in the overlap region, enabling the transistor to maintain proper electrical characteristics even with reduced overall size. This local structural enhancement allows smaller transistor footprint while preserving on-current performance
Data Source
AI summary
A thin film transistor includes a substrate, a gate electrode, a buffer layer, a gate insulating layer, an active layer, an etching stop layer, a source electrode and a drain electrode. The gate electrode is formed on the substrate. The buffer layer partially covers both side portions of the gate electrode. The gate insulating layer covers the gate electrode and the buffer layer. The active layer is formed on the gate insulating layer. The etching stop layer is formed on the active layer, and has a first opening and a second opening on the active layer. The source electrode is formed on the etching stop layer, and contacts with the active layer through the first opening. The drain electrode is formed on the etching stop layer, and is contacted with the active layer through the second opening.