TFT Array Substrate Capacitor Layout for Stable Gradation Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing thin-film transistor array substrates face challenges in maintaining capacitance while increasing the length of the semiconductor layer, which affects the performance and gradation control of display devices.
Innovation Solution
The design incorporates a thin-film transistor array substrate with a semiconductor layer of increased length, featuring a storage capacitor with a unique upper electrode structure having recessed portions that expose edges of the lower electrode, maintaining capacitance and allowing for precise control of the driving channel area, thereby reducing current changes due to voltage variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the length of the semiconductor layer is increased to improve gradation control, then the channel area increases, but the capacitance of the storage capacitor decreases
Solution Approach 1:
The upper electrode is designed with recessed portions that expose edges of the lower electrode, creating a multi-dimensional overlapping structure. This allows the electrode arrangement to extend in multiple directions rather than a simple planar overlap, effectively increasing the capacitance without requiring additional horizontal space that would conflict with the extended semiconductor layer.
Solution Approach 2:
The upper electrode is segmented into multiple portions separated by recessed areas, allowing different segments to overlap with different portions of the lower electrode. This segmentation enables the capacitance to be distributed across multiple overlapping regions, maintaining total capacitance while accommodating the longer semiconductor layer structure.
2Reliability
If the semiconductor layer length is increased to reduce current changes due to voltage variations, then the channel area increases, but the area available for the storage capacitor decreases
Solution Approach 1:
The electrode structure utilizes vertical and lateral dimensions creatively through recessed portions, allowing the storage capacitor to maintain sufficient area despite the reduced planar space caused by the extended semiconductor layer.
Solution Approach 2:
The recessed portions of the upper electrode are nested within the overall electrode structure, creating an efficient use of space where the electrode layers overlap in a nested configuration that maximizes capacitance within the available area.
3Reliability
If the upper electrode completely covers the lower electrode to maximize capacitance, then the capacitance increases, but the edge exposure needed for channel area definition is lost
Solution Approach 1:
The upper electrode is segmented with recessed portions that strategically expose edges of the lower electrode, allowing simultaneous achievement of high capacitance through overlapping areas and precise channel definition through exposed edges.
Solution Approach 2:
Different regions of the electrode structure have different functions: some regions are designed for maximum overlap to provide capacitance, while other regions with exposed edges are designed for precise channel area definition, creating local quality variations that satisfy multiple requirements.
Data Source
AI summary
A thin-film transistor array substrate includes a substrate, a thin-film transistor disposed on the substrate, where the thin-film transistor includes a semiconductor layer including a channel area and a gate electrode overlapping the channel area, and a storage capacitor including a lower electrode disposed on the channel area and an upper electrode disposed to overlap the lower electrode, where an opening having a single closed curve-shape is defined through the upper electrode. On a plane, the upper electrode includes a first recessed portion and a second recessed portion, each exposing an edge of the lower electrode.