TFT Array Capacitor Design for Narrow Frame Displays
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Solution Overview
Problem
The size of the capacitor in existing TFT array substrates is too large, restricting the development of narrow frame designs in liquid crystal display technology, as it occupies a significant area and requires a hollowed-out design for UV curing of the frame sealing glue, which increases the capacitor's size by about 50%.
Innovation Solution
The capacitor is formed by two sub-capacitors connected in parallel, using the TFT gate layer and ITO layers as electrodes, with a reduced dielectric layer thickness between them, allowing for a more compact design without compromising capacitance, and utilizing transparent ITO electrodes to eliminate the need for a hollowed-out structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a traditional capacitor structure with metal electrodes is used, then the capacitance can be achieved, but the capacitor area becomes too large and requires a hollowed-out design for UV curing
Solution Approach 1:
The patent changes the material parameter of the electrodes from opaque metal to transparent ITO (indium tin oxide), which fundamentally alters the optical properties and allows UV light transmission. This parameter change enables the capacitor to maintain its area without hollowing out while still allowing UV curing of the sealing glue from the TFT side
Solution Approach 2:
The ITO layer serves dual functions: as an electrode material providing the required capacitance and as a transparent material allowing UV light transmission. This multi-functionality eliminates the need for the hollowed-out design while maintaining both electrical and optical requirements
2Area of stationary object
If the capacitor area is reduced for narrow frame design, then the frame can be narrowed, but the capacitance may be compromised
Solution Approach 1:
The patent reduces the dielectric layer thickness parameter from conventional values to a specific range (2000-2500 Å), which increases the capacitance density. This parameter change allows the capacitor to maintain sufficient capacitance with a smaller area, enabling narrow frame design without compromising the shift register function
3Area of stationary object
If the dielectric layer thickness is reduced to decrease capacitor area, then the capacitor becomes more compact, but the manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a controlled thickness range of 2000-2500 Å for the dielectric layer, which balances the need for compact size with manufacturability. This parameter range is thin enough to reduce capacitor area significantly but thick enough to be controlled within acceptable manufacturing tolerances using standard deposition techniques
Data Source
AI summary
The present invention discloses a capacitor for a TFT array substrate and a method of manufacturing the same, and the present invention further discloses a shift register, a gate driver, an array substrate and a display device using the capacitor. The TFT array substrate comprises a TFT gate layer, a gate insulation layer, a first ITO layer, a TFT active layer, a TFT source-drain layer, a passivation layer and a second ITO layer formed sequentially on a glass substrate, and the capacitor is consisted of the first ITO layer, the passivation layer and the second ITO layer. In addition, the second ITO layer is connected with the TFT gate layer in a region where the capacitor is located, thereby forming two capacitors connected in parallel; or, the first ITO layer is connected with the TFT gate layer in the region where the capacitor is located, thereby also forming two capacitors connected in parallel. With the present invention, a space occupied by the capacitor for the TFT array substrate is reduced, and a size of the shift register is reduced, so as to be suitable for a narrow frame design.