TFT Storage Capacitor Layout for Overlay-Stable OLED Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In OLED displays, overlay deviations between the electrodes of the storage capacitor can occur due to misalignment during the patterning process, leading to variations in capacitance and resulting in issues like low-gradation spots and abnormal colors.
Innovation Solution
A TFT array substrate with a storage capacitor structure is designed, where the upper electrode overlaps the whole lower electrode and has an opening, ensuring that the capacitance remains substantially constant even with overlay deviations. This is achieved through a specific configuration of insulation layers, contact holes, and connection nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional capacitor structure with two patterned electrodes is used, then the manufacturing process follows standard photolithography procedures, but overlay deviation occurs between electrodes leading to capacitance variation
Solution Approach 1:
The capacitor structure is segmented into three parts: first electrode, second electrode, and third electrode. The first and third electrodes are formed in the same photolithography step, ensuring perfect alignment between them. The second electrode is formed separately but is positioned to overlap both first and third electrodes, creating a robust structure that tolerates overlay deviations.
Solution Approach 2:
The first and third electrodes are merged into a single conductive pattern formed in one photolithography step. This merging ensures that these two electrodes maintain precise relative positioning, while the second electrode serves as a common reference that overlaps both, effectively combining alignment benefits with manufacturing simplicity.
2Reliability
If the upper electrode completely covers the lower electrode, then overlay deviation tolerance is improved, but the capacitor occupies more area
Solution Approach 1:
The capacitor structure transitions from a planar two-electrode design to a three-dimensional overlapping configuration with three electrodes. The second electrode extends in the vertical dimension to overlap both first and third electrodes, achieving better overlay tolerance while managing area through vertical stacking rather than horizontal expansion.
Solution Approach 2:
The first and third electrodes are nested within the overlap region of the second electrode. This nested configuration allows the capacitor to achieve robust overlay tolerance through the overlapping structure while efficiently utilizing the available area by having the first and third electrodes fit within the footprint of the second electrode.
Data Source
AI summary
A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode and having an opening, and the upper electrode is insulated from the lower electrode by a second insulation layer; an inter-layer insulation film covering the capacitor; a node contact hole in the inter-layer insulation film and the second insulation layer, and within the opening; and a connection node on the inter-layer insulation film and electrically coupling the lower electrode and at least one TFT to each other through the node contact hole.