Thin-Film Transistor Capping Layer for Mobility Without Process Complexity
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Solution Overview
Problem
Existing thin film transistor manufacturing methods face increased process complexity and potential distortion of transfer curves, while aiming to improve mobility and performance in low gray level regions.
Innovation Solution
A thin film transistor design with a capping layer formed between the source and drain electrodes, using materials like aluminum oxide or silicon oxide, controlling carrier concentration and adjusting the capping layer's thickness and position to enhance mobility and subthreshold swing (SS).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capping layer is formed by repeatedly laminating channel layers and capping layers using ALD, then the mobility of the thin film transistor is improved, but the complexity of the process increases exponentially
Solution Approach 1:
The invention applies segmentation by forming only a partial capping layer in specific regions (such as the source region or drain region) rather than laminating capping layers throughout the entire channel. This selective placement reduces the number of deposition cycles needed while still achieving the desired mobility improvement in critical areas, thereby lowering process complexity compared to full-channel alternating lamination.
Solution Approach 2:
The invention implements local quality by concentrating the capping layer formation in specific regions (source or drain regions) where carrier concentration control is most beneficial for mobility enhancement. Rather than uniformly applying capping layers across the entire device, the partial capping approach targets only the regions that contribute most to performance, reducing overall process steps while maintaining effectiveness.
2Reliability
If aluminum oxide is applied on a thin film transistor using EHD jet printing, then the performance in low gray level region is improved, but the complexity of the process increases and the transfer curve may be distorted
Solution Approach 1:
The invention extracts the essential function of carrier concentration control from the complex EHD jet printing process by using a simpler partial capping layer approach. Instead of applying aluminum oxide through the specialized EHD process, the invention forms a partial capping layer using standard deposition techniques, achieving the same low gray level performance improvement without the process complexity and transfer curve distortion issues.
Solution Approach 2:
The invention replaces the complex, specialized EHD jet printing process with a more straightforward partial capping layer formation method. This substitution uses conventional deposition techniques that are already integrated into standard TFT manufacturing lines, eliminating the need for additional specialized equipment and process steps while achieving comparable or superior performance.
3Reliability
If a partial capping layer is formed to control carrier concentration, then mobility is enhanced, but the precision of carrier concentration control must be maintained
Solution Approach 1:
The invention applies preliminary action by carefully designing the partial capping layer parameters (thickness, area, and position) before fabrication to pre-determine the carrier concentration in the channel. By optimizing these parameters in advance based on device specifications, the invention achieves precise carrier concentration control without requiring complex in-process adjustments, thereby maintaining manufacturing precision while enhancing mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method reduces process complexity, maintains transfer curve integrity, and improves mobility and performance in low gray level regions, achieving high mobility and controlled SS.
Implementation Method 1
when forming each of them, a process such as vacuum deposition, sputtering, chemical vapor deposition, atomic layer deposition and the like is used
Data Source
AI summary
The thin film transistor according to one example of the present invention may comprise; a substrate; a gate electrode formed on the substrate; an insulating layer formed on the substrate to cover the gate electrode; a semiconductor layer formed on the insulating layer to form a channel; a source electrode and a drain electrode formed spaced apart from each other on the semiconductor layer; and a capping layer formed in at least one region between the source electrode and the drain electrode on the semiconductor layer to control the carrier concentration of the channel.