Thin Film Transistor Capping Layer Planarization
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Solution Overview
Problem
As display devices require high charge mobility in thin film transistors, increasing the grain size of the active layer through annealing leads to large protuberances at grain boundaries, causing electric field concentration and instability in device performance, affecting reliability.
Innovation Solution
A thin film transistor design with an active layer having a first portion of one thickness and a second portion of greater thickness, where a capping layer fills the thickness difference and is arranged on the first portion, along with a gate insulating layer and electrodes, to alleviate electric field concentration. The manufacturing process involves forming an amorphous silicon layer, crystallizing it with a protuberance, and then polishing to create a planarized active layer with a capping layer as a protective surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capping layer is formed to protect the active layer surface, then device reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines the protective capping layer function with the surface planarization process. The capping layer is formed to cover and protect the active layer, and simultaneously serves as the surface that will be polished to remove protuberances. This merging of functions provides protection while managing process complexity through integration.
Solution Approach 2:
The capping layer is formed in advance before the polishing step, providing protective coverage during subsequent manufacturing processes. This preliminary action ensures the active layer is protected from damage while allowing the protuberance removal to proceed, resolving the contradiction between protection and process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces grain boundary protuberances, stabilizes electric characteristics, and enhances the reliability of the thin film transistor and display device by maintaining a protective capping layer during manufacturing, ensuring improved charge mobility and reduced electric field concentration.
Implementation Method 1
The active layer in an amorphous state is formed over a substrate and then crystallized through an appropriate heat treatment process
Implementation Method 2
a method is used in which an amorphous silicon layer is formed first, a capping layer covers the amorphous silicon layer, and then annealing is performed to increase a heating efficiency
Implementation Method 3
a chemical mechanical polishing process is performed on the crystalline silicon layer to remove a protuberance at a grain boundary
Data Source
AI summary
A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.