Compositionally Modulated TFT Capping Layer for Low Contact Resistance
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Solution Overview
Problem
Current transistors with semiconducting metal oxide materials face issues such as short channel effects, back channel leakage current, and high contact resistance due to surface defects and interface trap densities, which degrade current-voltage characteristics and reliability.
Innovation Solution
An active layer of semiconducting metal oxide material is formed with an in-process capping layer of dielectric metal oxide, which reduces interface trap density and is converted into conductive material portions to lower contact resistance and interfacial trap density, improving transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a simple capping layer is used, then the manufacturing process is simple, but interface trap density remains high causing back channel leakage current
Solution Approach 1:
The capping layer is segmented into multiple layers with different compositions and functions: a first capping layer (e.g., aluminum oxide) provides high-quality interface with low trap density, while a second capping layer (e.g., silicon oxide) provides etch selectivity and protection. This segmentation resolves the contradiction by achieving low interface trap density through the first layer while maintaining manufacturing simplicity through standardized deposition processes for each layer.
Solution Approach 2:
The patent uses composite capping layer structures combining different dielectric materials (e.g., aluminum oxide and silicon oxide, or hafnium oxide and silicon nitride) to achieve properties that single materials cannot provide. The composite structure provides both low interface trap density from one material and etch selectivity or mechanical protection from another, resolving the contradiction between reliability and ease of manufacture.
2Ease of manufacture
If conventional capping materials are used, then processing is straightforward, but contact resistance remains high
Solution Approach 1:
The patent applies different materials or compositions to different regions or depths of the capping layer structure. For example, the first capping layer in direct contact with the semiconductor active layer is optimized for interface quality and low trap density, while the second capping layer is optimized for etch selectivity and mechanical properties. This local differentiation resolves the contradiction by ensuring each region has the optimal properties for its specific function.
3Length of moving object
If thin capping layers are used, then short channel effects are reduced, but interface defects increase causing leakage current
Solution Approach 1:
The patent forms high-quality capping layers with low interface trap density before subsequent processing steps that could introduce defects. The first capping layer is deposited and optimized to provide a clean, low-trap interface with the semiconductor active layer before any etching or patterning occurs. This preliminary action of establishing a high-quality interface early in the process resolves the contradiction by preventing interface defects from forming, even when thin channel structures are subsequently created.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and enhances transistor performance by minimizing interface defects and contact resistance, thereby improving the reliability and current-voltage characteristics of thin-film transistors.
Implementation Method 1
the dielectric metal oxide material provides an interfacial trap density that is less than 5×1011/(cm2 eV) at an interface with an overlying insulating material
Implementation Method 2
conductive material portions that underlie respective source and drain structures, wherein the conductive material portions lower contact resistance
Data Source
AI summary
A reduced interfacial defect density and low contact resistance can be provided for a thin film transistor by using a compositionally-modulated capping layer. A stack including a gate electrode, a gate dielectric layer, an active layer including a semiconducting metal oxide material, an in-process capping layer including a dielectric metal oxide material can be formed over a substrate. A dielectric material layer can be formed, and a source cavity and a drain cavity can be formed through the dielectric material layer. Exposed portions of the in-process capping layer can be converted into conductive material portions to provide a compositionally-modulated capping layer, which includes a first conductive capping material portion, the second conductive capping material portion, and a dielectric capping material portion.