Thin Film Transistor Carrier Injection Layer Contact Resistance
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Solution Overview
Problem
Thin film transistors (TFTs) face issues with conductive properties due to unintentional oxidation of the source/drain-electrode layer during high temperature treatment, leading to increased contact resistance and reduced on-current, despite the use of buffer layers to protect the electrode layer.
Innovation Solution
Incorporating a carrier injection layer at the bottom of the source/drain-electrode layer, in direct contact with the gate insulator layer and the semiconductor layer, and combining it with a protection layer on top of the source/drain-electrode layer to prevent oxidation during the annealing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a buffer layer is introduced between the source/drain-electrode layer and the active semiconductor layer to protect the electrode layer, then oxidation of the electrode layer is reduced, but the contact resistance between the electrode layer and semiconductor layer increases
Solution Approach 1:
An injection layer is introduced as an intermediary between the source/drain electrode layer and the active semiconductor layer. This injection layer serves as a mediator that facilitates carrier transport while preventing direct contact between the electrode and semiconductor, thereby reducing contact resistance without compromising protection from oxidation.
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different functional properties: the buffer layer provides oxidation protection, while the injection layer enables efficient carrier injection. This composite material approach allows simultaneous achievement of protection and low contact resistance.
2Manufacturing precision
If high temperature treatment is applied during fabrication to form the semiconductor laminate, then the active oxide semiconductor layer is formed, but the source/drain-electrode layer surface is unintentionally oxidized
Solution Approach 1:
The buffer layer is deposited on the source/drain electrode layer before the high temperature treatment that forms the active oxide semiconductor layer. This preliminary protective action prevents oxidation of the electrode layer during the subsequent thermal processing required for semiconductor layer formation.
Solution Approach 2:
The buffer layer acts as an intermediary barrier between the source/drain electrode layer and the oxidizing atmosphere during high temperature treatment, allowing the semiconductor layer to be formed while protecting the electrode from oxidation.
3Object-affected harmful factors
If the buffer layer is positioned above the source/drain-electrode layer and beneath the active semiconductor layer, then vertical protection is provided, but horizontal influences during laminate alignment still cause oxidation at the side surface
Solution Approach 1:
The patent extends protection from a single vertical layer to a three-dimensional network by having the semiconductor layer contact multiple surfaces (gate insulator layer, injection layer, and source/drain electrode layer). This multi-dimensional contact configuration ensures protection and low contact resistance at all interfaces, including side surfaces.
Solution Approach 2:
The contact interface is segmented into multiple contact points: the semiconductor layer contacts the gate insulator layer, the injection layer, and the source/drain electrode layer at different locations. This segmentation ensures that oxidation at any single interface does not compromise overall device performance.
Data Source
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AI summary
The present invention relates to a novel thin film transistor (TFT) comprising a substrate (100) with a gate electrode layer (101) deposited and patterned thereon and a gate insulator layer (102) deposited on the gate electrode layer and the substrate, characterized in that the transistor further comprises (i) a carrier injection layer (103) arranged above the gate insulator layer, (ii) a source/drain (S/D) electrode layer (104) deposited on the carrier injection layer, and (iii) a semiconductor layer (106), methods for the production of such novel TFTs, devices comprising such TFTs, and to the use of such TFTs.