Thin Film Transistor Metal Catalyst Concentration Control
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Solution Overview
Problem
Existing methods for crystallizing amorphous silicon into polycrystalline silicon for thin film transistors, such as SPC and ELC, face issues like long process times, high temperatures, substrate deformation, and inferior interfacial characteristics, while metal-induced crystallization methods struggle with metal catalyst remnants in the channel region increasing leakage current.
Innovation Solution
Adjusting the concentration of the metal catalyst in the channel region of the semiconductor layer to be between 0 and 6.5×E17 atoms per cm3 within 150 Å, using methods like MIC, MILC, or SGS, to control grain size and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal catalyst is used to crystallize amorphous silicon layer, then crystallization temperature is reduced and process time is shortened, but metal catalyst remains in channel region and increases leakage current
Solution Approach 1:
The patent applies local quality by creating different metal catalyst concentration zones within the semiconductor layer. The channel region maintains low metal catalyst concentration (≤6.5×10^17 atoms/cm³) to minimize leakage current, while other regions can have higher concentrations to facilitate crystallization. This spatial differentiation of metal catalyst distribution allows the system to achieve both rapid crystallization and low leakage current by optimizing metal catalyst presence locally rather than uniformly throughout the layer.
2Ease of manufacture
If metal catalyst concentration in channel region is increased to improve crystallization, then crystallization efficiency is improved, but leakage current increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the metal catalyst concentration parameter within the channel region to be ≤6.5×10^17 atoms/cm³. This specific parameter threshold optimizes the balance between crystallization efficiency and leakage current. The patent achieves this by adjusting deposition conditions, annealing parameters, or metal catalyst layer thickness to maintain the concentration within the specified range, thereby enabling efficient crystallization while suppressing harmful leakage current effects.
3Reliability
If SPC method is used for crystallization, then polycrystalline silicon layer is formed, but process time is long and substrate deformation occurs
Solution Approach 1:
The patent applies the intermediary principle by introducing a metal catalyst layer as a mediator between the amorphous silicon layer and the crystallization process. Instead of directly heating the amorphous silicon to high temperatures for extended periods (SPC method), the metal catalyst facilitates crystallization at lower temperatures and shorter times by forming intermediate metal-silicon compounds that promote crystal nucleation and growth. This intermediary mechanism enables rapid crystallization without the time loss and substrate deformation issues of conventional SPC.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in thin film transistors with excellent electrical characteristics by maintaining a low leakage current, ensuring the metal catalyst concentration within the specified range does not exceed 6.5×E17 atoms per cm3, thereby enhancing the transistor's performance.
Implementation Method 1
In the MIC method, metals such as nickel, palladium, gold, aluminum, etc., are placed in contact with an amorphous silicon layer or are injected, so that the amorphous silicon layer is changed into a polycrystalline silicon layer, i.e., a phase change is induced
Implementation Method 2
In the MILC method, silicide, which is generated by reacting metal with silicon, is laterally and continuously diffused to sequentially induce crystallization of the amorphous silicon layer
Data Source
AI summary
A thin film transistor includes a substrate, a semiconductor layer disposed on the substrate, including a channel region and source and drain regions and crystallized using a metal catalyst, a gate electrode disposed to correspond to a predetermined region of the semiconductor layer, a gate insulating layer disposed between the gate electrode and the semiconductor layer to insulate the semiconductor layer from the gate electrode, and source and drain electrodes electrically connected to the source and drain regions of the semiconductor layer, respectively. The metal catalyst within 150 Å from a surface of the semiconductor layer in a vertical direction is formed to have a concentration exceeding 0 and not exceeding 6.5×E17 atoms per cm3 in the channel region of the semiconductor layer. An organic light emitting diode (OLED) display device includes the thin film transistor.