TFT Array Substrate Channel Doping for OLED Residual Shadow Reduction

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Solution Overview

Problem

Active matrix OLED display panels experience residual shadows due to uneven brightness across different areas when switching between gray scales, affecting visual quality.

Innovation Solution

A thin film transistor (TFT) array substrate with a semiconductor layer doped with a p-type impurity of molecular weight equal to or greater than 25 in the channel region, and a doping depth ranging from 1 nm to 20 nm, improving electrical consistency and stability of TFTs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional doping methods are used in OLED display panels, then manufacturing process is simple, but residual shadow occurs due to uneven brightness across different areas

Engineering Contradiction:
Improvedisplay uniformityVSAvoiddoping process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by doping only the channel region of the semiconductor layer with p-type impurity, while leaving the source and drain regions undoped or differently doped. This localized doping approach targets specifically the area causing brightness non-uniformity (the channel region between source and drain), thereby improving display uniformity and reducing residual shadow effects without requiring complete restructuring of the entire device.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the doping parameter by using p-type impurity with molecular weight of 25 or more (such as boron with molecular weight 10.8, or more preferably heavier elements like aluminum with molecular weight 27.0). This parameter change in impurity selection and doping depth (1-20 nm) optimizes the electrical properties of the channel region, improving carrier mobility and reducing threshold voltage shifts that cause residual shadow, thereby enhancing display uniformity.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If p-type impurity doping is applied to improve electrical consistency, then display uniformity improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical consistencyVSAvoiddoping depth control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent specifies a doping depth range of 1-20 nm for the p-type impurity in the channel region, which is a carefully optimized parameter range. This parameter control ensures that the doping penetrates sufficiently to modify the electrical properties of the channel (improving electrical consistency) while not extending too deep to cause leakage or short circuits. The molecular weight specification (≥25) also serves as a controllable parameter that affects doping behavior and depth distribution.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs feedback mechanisms through precise control of doping parameters (molecular weight ≥25, depth 1-20 nm) based on measured electrical characteristics of the TFTs. By monitoring threshold voltage shifts and subthreshold swing characteristics after doping, the process can be adjusted to achieve the desired electrical consistency across different areas of the display panel, thereby managing manufacturing precision requirements.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces residual shadows and enhances display uniformity and visual quality by ensuring consistent luminance across different gray scales.

Implementation Method 1

The channel region is doped with a p-type impurity, a molecular weight of the p-type impurity in the channel region is equal to or greater than 25 and a range of a doping depth of the p-type impurity in the channel region is 1 nm to 20 nm

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS20220302321A1Thin film transistor array substrate, display panel and display device
Publication Date: 2022.09.22 KUNSHAN GO VISIONOX OPTO ELECTRONICS CO LTD
  • US20220302321A1 patent drawing
  • US20220302321A1 patent drawing
  • US20220302321A1 patent drawing

AI summary

A thin film transistor array substrate, a display panel and a display device. The thin film transistor array substrate includes a semiconductor layer, a gate layer and a source-drain layer arranged in a stacked manner, two insulating layers respectively located between the semiconductor layer and the gate layer and between the gate layer and the source-drain layer, the semiconductor layer comprises a source region, a drain region and a channel region located between the source region and the drain region, the channel region is doped with a p-type impurity, a molecular weight of the p-type impurity in the channel region is equal to or greater than 25, a range of a doping depth of the p-type impurity in the channel region is 1 nm to 20 nm.