Thin-Film Transistor Channel Doping to Reduce Trap De-Trap
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Solution Overview
Problem
Current thin-film transistors in display apparatuses face challenges in achieving high quality due to issues with dopant distribution and trap/de-trap phenomena, which affect the driving speed and reliability of the transistors.
Innovation Solution
A thin-film transistor substrate is designed with a semiconductor layer having a first dopant and a second dopant of different types, with specific concentration profiles and locations to minimize trap/de-trap phenomena, including a buffer layer, inorganic barrier layers, and a gate electrode overlapping the channel area, and a manufacturing method that involves injecting dopants with varying acceleration voltages to achieve optimal doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-dopant structure is used in the semiconductor layer, then the manufacturing process is simple, but undesired buried channels form and carrier trap/de-trap phenomena occur, reducing transistor quality
Solution Approach 1:
The semiconductor layer is segmented into multiple dopant regions: a first dopant is introduced into the substrate before forming the semiconductor layer, and a second dopant is doped into the semiconductor layer afterward. This segmentation allows distinct dopant concentration profiles (e.g., higher concentration at the interface, lower in the bulk) to be achieved, preventing buried channel formation and reducing carrier trap/de-trap phenomena while maintaining manufacturing feasibility through sequential processing steps.
Solution Approach 2:
Different dopant concentrations are applied to different regions of the semiconductor layer. The first dopant creates a specific concentration profile at the substrate interface, while the second dopant provides a different concentration within the semiconductor layer bulk. This local quality variation optimizes carrier transport at critical interfaces while maintaining appropriate bulk properties, thereby improving transistor quality without requiring complex overall device architecture.
2Speed
If dopant concentration is increased to improve transistor performance, then driving speed improves, but carrier trap/de-trap phenomena increase, reducing overall quality
Solution Approach 1:
The patent applies different dopant concentrations to different regions: the first dopant is introduced at a first concentration into the substrate, and the second dopant is doped at a second concentration into the semiconductor layer. This local quality variation allows high doping concentrations to be used selectively at the substrate interface to enhance carrier transport speed, while maintaining lower concentrations in the bulk semiconductor layer to minimize carrier trap/de-trap phenomena, thus simultaneously improving driving speed and carrier transport stability.
Solution Approach 2:
The patent changes the dopant concentration parameter across different regions and layers. By controlling the first dopant concentration in the substrate and the second dopant concentration in the semiconductor layer separately, the invention optimizes the balance between driving speed (requiring higher doping) and carrier transport stability (requiring lower doping to reduce traps), achieving both improved speed and reliability through parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces carrier trap/de-trap phenomena, enhances the driving speed of the thin-film transistor, and prevents the formation of undesired buried channels, leading to improved performance and reliability of the display apparatus.
Implementation Method 1
a first dopant doped in an upper portion of the channel area at a first concentration; a second dopant doped in a lower portion of the channel area at a second concentration
Data Source
AI summary
Provided are a thin-film transistor substrate, a manufacturing method thereof, and a display apparatus. The thin-film transistor substrate includes: a substrate; a buffer layer on the substrate; a semiconductor layer arranged on the buffer layer and including a first conductive area, a second conductive area, and a channel area between the first conductive area and the second conductive area; a first dopant doped in an upper portion of the channel area at a first concentration; a second dopant doped in a lower portion of the channel area at a second concentration and being of a different type from a type of the first dopant; a gate insulating layer covering the semiconductor layer; and a gate electrode overlapping the channel area in a plan view and disposed on the gate insulating layer.