Thin-Film Transistor Channel Layout for High-Resolution Display Panels
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Solution Overview
Problem
Current mini/micro LED displays face challenges in achieving high-resolution displays due to the difficulty in reducing the size of thin-film transistors with short channels, as the lengths of channel regions are determined by gate electrodes, making it hard to miniaturize the transistors effectively.
Innovation Solution
The display panel incorporates a thin-film transistor with an active portion comprising a conductor sublayer and a semiconductor sublayer, where the conductor sublayer has isolated subsections, allowing for a shorter channel length through precise photolithography, and includes a gate electrode positioned above the active layer to improve current passing capacity and mobility, reducing transistor size and increasing resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If channel region length is determined by gate electrode length, then transistor structure is simple to manufacture, but transistor size cannot be reduced effectively
Solution Approach 1:
The conductor sublayer is segmented into a first conductor subsection and a second conductor subsection that are spaced apart from each other. This segmentation allows the channel region to be defined by the gap between these subsections rather than by the gate electrode length, enabling independent control of channel length and gate length. The isolated conductor subsections create a precise channel region through photolithography, achieving ultra-short channel lengths while maintaining manufacturing feasibility.
2Ease of manufacture
If channel region length is determined by gate electrode length, then manufacturing process is straightforward, but high resolution display cannot be achieved
Solution Approach 1:
By segmenting the conductor sublayer into isolated subsections, the channel region length can be precisely controlled through photolithography patterns. This allows for ultra-short channel lengths that enable higher pixel density and display resolution, while the manufacturing process remains relatively straightforward using standard photolithography techniques.
Solution Approach 2:
The patent replaces the mechanical/dimensional constraint of gate electrode length with a photolithography-defined conductor pattern. Instead of relying on the physical length of the gate electrode to define the channel, the channel region is defined by the spaced-apart conductor subsections created through photolithography, enabling more precise control over channel dimensions.
Data Source
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AI summary
A display panel and a method of manufacturing the same, and a display device are provided. A first metal layer (20) is disposed on a substrate (10) and includes a source electrode (21) and a drain electrode (22). An active layer is disposed on a side of the first metal layer (20) away from the substrate (10) and includes an active portion (30). The active portion (30) includes a conductor sublayer (31) and a semiconductor sublayer (32). The conductor sublayer (31) includes a first conductor subsection (311) and a second conductor subsection (312) spaced apart from each other, and the semiconductor sublayer (32) is connected at least between the first conductor subsection (311) and the second conductor subsection (312).