Thin Film Transistor Clamping Structure for Low Power
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Solution Overview
Problem
Current thin film transistor liquid crystal display (TFT LCD) technologies face limitations in reducing power consumption while maintaining high image quality and performance, as existing methods to improve Ohmic contact resistance are insufficient.
Innovation Solution
The TFT design incorporates a semiconductor layer with a sandwich structure where the source and drain clamp both ends, increasing the Ohmic contact area and channel width, thereby reducing operation voltage and power consumption, and optimizing electrode positions to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an Ohmic contact layer is disposed on the contact surfaces of the semiconductor layer and the source (or the drain), then the Ohmic contact resistance is reduced, but the power consumption reduction effect is limited
Solution Approach 1:
The source and drain electrodes are extended to clamp both ends of the semiconductor layer, transitioning from a single-plane contact to a three-dimensional clamping structure. This multi-dimensional contact arrangement significantly increases the Ohmic contact area and reduces contact resistance more effectively than conventional single-layer approaches, thereby achieving better power consumption reduction.
Solution Approach 2:
The source and drain electrodes are merged with the semiconductor layer ends to form an integrated clamping structure. This merging increases the contact area between the electrodes and the semiconductor layer, improving Ohmic contact and reducing power consumption more effectively than separate contact layers.
2Use of energy by moving object
If the source and drain clamp both ends of the semiconductor layer to increase Ohmic contact area, then power consumption is reduced, but the device structure becomes more complex
Solution Approach 1:
The source and drain are segmented into multiple electrode portions that respectively clamp different ends of the semiconductor layer. This segmentation allows each electrode portion to be optimized independently for its specific contact region, achieving low power consumption through increased contact area while maintaining manufacturing feasibility through modular structure design.
Solution Approach 2:
The source and drain electrodes serve multiple functions: they provide electrical connection, clamp the semiconductor layer to increase contact area, and contribute to parasitic capacitance minimization through optimized positioning. This multi-functionality reduces the need for additional separate components, balancing structural complexity with performance benefits.
3Productivity
If the source and drain clamp both ends of the semiconductor layer, then the channel width is increased and current transmission is improved, but the parasitic capacitance may increase
Solution Approach 1:
Different regions of the source and drain electrodes are positioned with different qualities in mind: the electrode portions contacting the semiconductor layer ends are optimized for maximum Ohmic contact to improve current transmission, while the electrode portions in the channel region are optimized for minimal overlap with the gate to reduce parasitic capacitance. This local quality differentiation resolves the contradiction between current transmission and parasitic capacitance.
Solution Approach 2:
The positions and dimensions of the source and drain electrodes are precisely controlled within specific parameter ranges. The electrode width, length, and spacing are optimized to achieve sufficient contact area for low resistance while maintaining minimal parasitic capacitance. Parameter optimization allows simultaneous improvement of current transmission and control of parasitic effects.
Data Source
AI summary
A thin film transistor (TFT) is provided, which includes a gate, a semiconductor layer, an insulation layer, a source and a drain. The semiconductor layer has a first end and a second end opposite to the first end. The insulation layer is disposed between the gate and the semiconductor layer. The source clamps the first end of the semiconductor layer and the drain clamps the second end of the semiconductor layer.