Transition Fault Test Clock Receiver System
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Solution Overview
Problem
As clock frequencies increase, clock signal generators often experience instability, leading to missing pulses or insufficient amplitude, which can result in failure of transition fault tests (TFTs) in modern digital computing systems.
Innovation Solution
A clock receiver system with a scan clock generator that produces a scan clock signal with a pulse sequence including preliminary pulses with longer widths than periodic pulses, allowing the receiver logic to identify and successfully pass the TFT by mitigating distortion effects on initial pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to improve processing speed, then productivity is improved, but clock signal stability deteriorates causing missing pulses or insufficient amplitude
Solution Approach 1:
The patent applies preliminary action by inserting preliminary pulses before the actual capture window in the scan clock signal sequence. These preliminary pulses are generated in advance to condition the clock receiver and ensure it is properly synchronized and ready to detect the subsequent capture pulses, thereby preventing detection failures due to initial instability at high clock frequencies
Solution Approach 2:
The patent applies parameter changes by modifying the scan clock signal parameters, specifically by varying the pulse width and timing characteristics. The preliminary pulses have different timing parameters compared to the capture pulses, allowing the system to adapt the clock signal characteristics to ensure reliable detection at high frequencies while maintaining the required processing speed
2Reliability
If preliminary pulses with longer widths are added to mitigate distortion effects, then clock signal stability is improved, but device complexity increases
Solution Approach 1:
The patent applies periodic action by structuring the scan clock signal as a periodic sequence containing preliminary pulses followed by capture pulses within a defined capture window. This periodic structure with predetermined timing relationships simplifies the generation and detection logic, as the receiver can be configured to expect and detect pulses at regular intervals, thereby improving detection reliability without significantly increasing device complexity
Data Source
AI summary
One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.