TFT Array Substrate Common Electrode Resistance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing TFT array substrates have high resistance values in common electrode layers, leading to flicker and crosstalk issues, which affect picture quality, and previous solutions either reduce aperture ratio or increase production costs.
Innovation Solution
The implementation of common electrode lines in parallel with the common electrode layer through via holes, combined with a metal or alloy layer in direct contact, reduces the resistance of the common electrode layer without compromising the aperture ratio or increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal line is designed in parallel with a gate line on the same layer to reduce the resistance value of the common electrode layer, then the resistance value is reduced, but the edge distance of pixels is greatly affected and the aperture ratio declines
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked structure by placing common electrode lines on a different layer (below the pixel electrodes) and connecting them through via holes. This vertical arrangement allows the common electrode lines to run parallel to gate lines without occupying the same planar space, thus reducing resistance while preserving aperture ratio.
Solution Approach 2:
The common electrode layer is segmented into multiple common electrode lines that are distributed across different layers. By dividing the common electrode function into multiple conductive paths at different vertical levels, the overall resistance is reduced without requiring additional planar space that would compromise pixel aperture.
2Reliability
If a metal layer is directly made on the common electrode layer in direct contact to reduce resistance, then the resistance value is reduced, but additional processes are required which increase production cost
Solution Approach 1:
The patent makes the pixel electrode layer serve a dual function: as the pixel electrode for display function and as the common electrode line layer for electrical connection. By integrating these two functions into a single layer, the need for separate common electrode lines and additional manufacturing processes is eliminated, reducing production cost while maintaining low resistance.
Solution Approach 2:
The patent merges the pixel electrode layer and common electrode line layer into a single integrated structure. The pixel electrodes and common electrode lines coexist in the same layer, sharing the same manufacturing process, which simplifies production and reduces costs compared to having separate layers for each function.
3Length of moving object
If the size of the TFT array substrate is reduced, then the display device becomes more compact, but the aperture ratio becomes harder to maintain while reducing common electrode layer resistance
Solution Approach 1:
The patent utilizes the vertical dimension to route common electrode lines below the pixel electrodes and connect through via holes. This three-dimensional arrangement allows for compact substrate sizing while maintaining sufficient space for both pixel electrodes and common electrode connections, thus preserving aperture ratio even as overall device size is reduced.
Data Source
Figure 1~2
Figure 3~4
AI summary
The present invention relates to the field of liquid crystal display and discloses a TFT array substrate and a manufacturing method thereof and a liquid crystal display device, which is aiming at lowering the resistance value of a common electrode and not deminishing the aperture ratio of pixels on the premise that the manufacturing cost is not additionally increased. The TFT array substrate includes: a substrate, a common electrode layer arranged on the substrate, a first insulating layer arranged on the common electrode layer and a plurality of pixel electrodes arranged in an array on the first insulating layer, wherein via holes penetrating through the first insulating layer are formed between adjacent pixels in some of a plurality of pixels, and common electrode lines are grown between rows and/or columns of pixels in some of the plurality of pixels, and in parallel with the common electrode layer below the first insulating layer through the via holes.