Thin-Film-Transistor Array Substrate with Compensation Electrode

Solution Overview

Problem

Conventional thin-film-transistor array substrates face increased resistance in signal lines due to attempts to reduce parasitic capacitance between the drain and gate electrodes, which affects the operation characteristics of thin-film transistors.

Innovation Solution

A thin-film-transistor array substrate design featuring a scan-signal line with a compensation electrode extending from its opposite side, matching the area of the opening in the gate electrode, and maintaining a distance greater than 3.5 micrometers from the data-signal line, to mitigate resistance increases while reducing parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If an opening is made in the gate electrode to reduce parasitic capacitance, then parasitic capacitance decreases, but resistance of the scan-signal line increases

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidresistance value

Core Design Contradiction:

Object-affected harmful factorsVSReliability

Solution Approach 1:

The gate electrode is segmented by introducing an opening that divides it into two separate conductive regions. This segmentation reduces the overlapping area with the drain electrode, thereby decreasing parasitic capacitance while maintaining the overall gate structure functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A compensation electrode is introduced as an intermediary element to compensate for the resistance increase caused by the opening in the gate electrode. The compensation electrode provides an additional conductive path that offsets the resistance penalty, ensuring the scan-signal line maintains acceptable electrical characteristics.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the gate electrode area is reduced by adding an opening, then parasitic capacitance is reduced, but the transmission speed of the scan-signal line is affected

Engineering Contradiction:

Improveparasitic capacitanceVSAvoidtransmission speed

Core Design Contradiction:

Object-affected harmful factorsVSSpeed

Solution Approach 1:

The gate electrode is segmented by introducing an opening that divides it into two separate conductive regions. This segmentation reduces the overlapping area with the drain electrode, thereby decreasing parasitic capacitance while maintaining the overall gate structure functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A compensation electrode is introduced as an intermediary element to compensate for the resistance increase caused by the opening in the gate electrode. The compensation electrode provides an additional conductive path that offsets the resistance penalty, ensuring the scan-signal line maintains acceptable electrical characteristics.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8867004B2Thin-film-transistor array substrate and manufacturing method thereof

Publication Date: 2014.10.21 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD

AI summary

The present invention discloses a thin-film-transistor array substrate and a manufacturing method thereof. The array substrate includes a thin-film transistor and a compensation electrode. A gate electrode of the thin-film transistor is a portion of a scan-signal line and has an opening, and the opening extends to a side of the scan-signal line. A drain electrode of the thin-film transistor is disposed correspondingly to the opening. A source electrode of the thin-film transistor extends from a side of a data-signal line and surrounds the drain electrode. The compensation electrode extends from another side of the scan-signal line and corresponds to the gate electrode. Therefore, the present invention is capable of reducing parasitic capacitance between the drain electrode and the gate electrode without increasing the resistance value of the scan-signal line.