TFT Conductive Layer Offset Area Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Polysilicon Thin Film Transistors experience reduced on-state currents due to an offset area between the gate and active layer, which increases carrier resistance and impairs current characteristics.
Innovation Solution
A conductive layer is disposed between the gate insulating layer and the gate, with its projection on the base substrate being larger than the gate's projection, ensuring electrical connection in the offset area and increased voltage application, thereby reducing carrier resistance and enhancing on-state currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional TFT structure with gate directly on gate insulating layer is used, then the device structure is simple, but the on-state current is reduced due to offset area carrier resistance
Solution Approach 1:
A conductive layer is introduced as an intermediary between the gate insulating layer and the gate electrode. This conductive layer extends into the offset area to provide additional electrical connection paths for carriers, reducing carrier resistance without significantly complicating the overall device structure.
Solution Approach 2:
The conductive layer is positioned in a different dimensional space (between the gate insulating layer and gate electrode) rather than modifying the gate electrode itself or the active layer, providing a new pathway for electrical connection that reduces carrier resistance in the offset area.
2Reliability
If the gate projection is made larger to cover the offset area, then carrier resistance is reduced, but the device area increases
Solution Approach 1:
The electrical connection function is segmented between the gate electrode and the conductive layer. The gate electrode maintains its original projection size, while the conductive layer separately extends into the offset area to provide electrical connection, avoiding the need to increase the gate electrode projection and thus preventing device area increase.
Data Source
AI summary
The present disclosure provides a Thin Film Transistor and a method for manufacturing the same, an array substrate and a display device, so as to increase on-state currents of the Thin Film Transistor and improve current characteristics of the Thin Film Transistor. The Thin Film Transistor includes a base substrate, a gate insulating layer and a gate disposed above the base substrate; wherein a conductive layer is also disposed between the gate insulating layer and the gate; wherein the projection of the conductive layer on the base substrate is larger than the projection of the gate on the base substrate.