Thin-Film Transistor Contact Structure for Low Leak Current
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Solution Overview
Problem
Conventional low-temperature polycrystalline silicon (LTPS) thin film transistors face challenges in achieving optimal ohmic contact and reducing leak current, which affects the performance and efficiency of display devices like LCD and OLED.
Innovation Solution
The thin film transistor design incorporates a polycrystalline silicon part and an amorphous silicon part, with a doped amorphous silicon layer acting as an ohmic contact layer, and an etch stop layer strategically positioned to cover both parts, enhancing the channel region and improving contact efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional LTPS thin film transistor structure is used with doped polysilicon contact region, then mobility rate is improved, but leak current increases and ohmic contact is not optimal
Solution Approach 1:
The contact region is segmented into two distinct parts: a first contact region with polysilicon having a first doping concentration, and a second contact region with polysilicon having a second doping concentration different from the first. This segmentation allows each region to be optimized for different functions - one for high mobility and the other for low leak current and optimal ohmic contact.
Solution Approach 2:
Different doping concentrations are applied to different spatial regions of the contact area. The first contact region uses one doping concentration to optimize for mobility, while the second contact region uses a different doping concentration to optimize for ohmic contact and reduce leak current. This local quality variation resolves the contradiction by allowing each region to have the specific property needed for its function.
2Ease of manufacture
If single doping concentration is used in contact region, then manufacturing is simplified, but ohmic contact efficiency is insufficient
Solution Approach 1:
The contact region is divided into multiple doped regions with different doping concentrations. This can be achieved through selective doping processes or by forming regions with different dopant types (e.g., n-type and p-type), thereby maintaining manufacturing feasibility while achieving optimal ohmic contact through localized property variation.
3Reliability
If polysilicon contact region is heavily doped to improve ohmic contact, then contact resistance decreases, but leak current increases
Solution Approach 1:
The contact structure is segmented into a first contact region optimized for ohmic contact with appropriate doping, and a second contact region with different doping characteristics that prevents leak current. This segmentation allows the system to achieve good ohmic contact without the harmful side effect of increased leak current that would result from uniform heavy doping.
Solution Approach 2:
Different doping concentrations or types are applied to different local regions of the contact area. One region is doped to achieve low contact resistance for optimal ohmic contact, while another region has different doping characteristics that prevent leak current generation, thus resolving the contradiction locally.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly lowers leak current and improves the migration rate of the thin film transistor, leading to better performance and efficiency in display devices.
Implementation Method 1
an etch stop layer on a side of the polycrystalline silicon part away from the base substrate; wherein an orthographic projection of the etch stop layer on the base substrate covers an orthographic projection of the polycrystalline silicon part on the base substrate
Data Source
AI summary
A thin film transistor is provided. The thin film transistor includes abase substrate; a gate electrode on the base substrate; an active layer on the base substrate, the active layer including a polycrystalline silicon part including a polycrystalline silicon material and an amorphous silicon part including an amorphous silicon material; a gate insulating layer insulating the gate electrode from the active layer; a source electrode and a drain electrode on the base substrate; and an etch stop layer on a side of the polycrystalline silicon part away from the base substrate. An orthographic projection of the etch stop layer on the base substrate covers an orthographic projection of the polycrystalline silicon part on the base substrate, and an orthographic projection of at least a portion of the amorphous silicon part on the base substrate.