TFT Substrate Copper Gate Line Organic Insulator

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Solution Overview

Problem

The increase in size and resolution of liquid crystal displays leads to increased resistance in metal wiring, causing RC delay, and copper wiring reacts with organic layers, potentially deteriorating the display.

Innovation Solution

A thin film transistor substrate with copper wiring and an organic insulating layer, where the gate electrode is formed on the organic insulator to prevent organic material adhesion, and a semiconductor made of an oxide including Zn, Ga, Sn, or In is used, along with a silicon oxide or nitride interlayer to reduce signal delay and prevent display deterioration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper wiring is used to reduce resistance, then electrical resistance decreases, but organic material is adsorbed on the copper surface causing display deterioration

Engineering Contradiction:
Improvedisplay qualityVSAvoidorganic material adhesion
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An organic insulating layer is introduced as an intermediary between the copper gate line and the semiconductor/organic layers. This mediator prevents direct contact and adsorption between copper and organic materials, eliminating display deterioration while preserving copper's low resistance properties

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate electrode is separated from the copper gate line by removing the direct interface and inserting an organic insulating layer. This extraction of the problematic copper-organic interface prevents harmful interactions while maintaining electrical functionality through the insulating layer

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If display size and resolution are increased, then display quality improves, but wiring resistance increases causing RC delay

Engineering Contradiction:
Improvedisplay qualityVSAvoidsignal delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the material parameter of the gate line from conventional materials to copper, which has significantly lower electrical resistance. This parameter change reduces RC delay and signal loss, enabling high-resolution displays while maintaining signal integrity across larger display areas

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution prevents display deterioration by reducing copper-organic interactions and signal delay, enabling high-quality thin film transistor substrates for liquid crystal displays.

Implementation Method 1

The copper wiring reacts with the organic layer, however, such that the organic material is adsorbed on the surface of the signal wiring. If this phenomenon is generated on the gate electrode when forming the gate wire made of the copper material, display deterioration may occur.

Methodology Applied
Scientific EffectAdsorption prevention: Adsorption

Implementation Method 2

a silicon oxide or nitride interlayer to reduce signal delay

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS8389998B2Thin film transistor array panel and method for manufacturing the same
Publication Date: 2013.03.05 SAMSUNG DISPLAY CO LTD
  • US8389998B2 patent drawing
  • US8389998B2 patent drawing
  • US8389998B2 patent drawing

AI summary

A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.