TFT Array Substrate Cover Metal Segmentation for High Resolution
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Solution Overview
Problem
The challenge in achieving high resolution in organic light emitting display devices is the limited space for pixel circuits due to the need for narrower signal wires and the restriction imposed by the size of cover metal, which affects the efficiency and resolution of the display.
Innovation Solution
A thin-film transistor (TFT) array substrate design that includes multiple insulation layers and specific metal configurations, such as using molybdenum for the cover metal and aluminum for signal wires, to optimize the size and resistance of signal wires and cover metal, allowing for reduced size and improved resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the size of cover metal is reduced to accommodate high resolution, then the resolution is improved, but the electrical connection reliability may deteriorate
Solution Approach 1:
The electrical connection path is segmented into multiple independent components: contact hole through first/third insulation layers, via hole through second insulation layer, and separate cover metal pattern. This segmentation allows each component to be optimized independently for both size and reliability.
Solution Approach 2:
The connection structure transitions from a single-plane metal pattern to a multi-layer three-dimensional structure with insulation layers sandwiched between conductive elements, enabling reduced cover metal size while maintaining connection integrity through vertical stacking.
2Manufacturing precision
If multiple insulation layers are added to separate signal wires and cover metal, then the resolution and efficiency are improved, but the device complexity increases
Solution Approach 1:
The second insulation layer serves multiple functions simultaneously: it electrically isolates the cover metal from the anode electrode, provides a planarization surface for subsequent layers, and enables the via hole connection structure. This multi-functionality reduces the need for additional dedicated layers.
Solution Approach 2:
The patent utilizes vertical layering to separate functions that would otherwise require horizontal separation, achieving wire and cover metal isolation through the Z-dimension (stacked layers) rather than increasing lateral complexity.
Data Source
AI summary
A TFT array substrate includes: a first insulation layer over a semiconductor layer; a second insulation layer over a plurality of first gate wires formed on the first insulation layer; a third insulation layer over a plurality of second gate wires formed on the second insulation layer; a cover metal formed over the third insulation layer and contacting the semiconductor layer through a contact hole that passes through the first, second and third insulation layers; a fourth insulation layer over the cover metal; a protection layer formed over the fourth insulation layer; and an anode electrode formed over the protection layer and contacting the cover metal through a via hole that passes through the protection layer, the fourth insulation layer, and the contact hole.