Thin Film Transistor With Curved Recess And Thickness Gradient
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Solution Overview
Problem
Thin film transistors, particularly those using polycrystalline silicon, face challenges in maintaining low channel resistance and high field-effect mobility due to uneven semiconductor film thickness on the sidewall and bottom surfaces, leading to increased channel resistance and limitations in improving performance.
Innovation Solution
A thin film transistor configuration with a semiconductor film having a curved recess portion, where the interlayer insulating film contains nitrides in higher amounts than the gate insulating film, and semiconductor crystalline nuclei formed on both films, including germanium, to enhance the thickness and crystallinity of the semiconductor film, thereby reducing channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional thin film transistor structure with uniform semiconductor film thickness is used, then the manufacturing process is simple, but the channel resistance increases and field-effect mobility decreases due to insufficient film thickness on sidewall surfaces
Solution Approach 1:
The patent applies local quality by creating a thickness-gradient semiconductor film where the film thickness varies spatially: thinner on the bottom surface and thicker on the sidewall surfaces. This localized thickness variation optimizes electrical performance by ensuring adequate carrier transport paths along the channel while maintaining proper gate control, thereby achieving high field-effect mobility without compromising manufacturing feasibility
Solution Approach 2:
The patent transitions from a two-dimensional uniform film concept to a three-dimensional thickness-gradient structure. By introducing vertical thickness variation across the film plane (different thicknesses on bottom vs. sidewall surfaces), the invention achieves superior electrical characteristics that cannot be obtained with conventional uniform thin films, effectively adding a dimensional aspect to film design
2Productivity
If the semiconductor film thickness is increased on sidewall surfaces to reduce channel resistance, then field-effect mobility improves, but the manufacturing complexity increases
Solution Approach 1:
The patent employs parameter changes by systematically controlling deposition conditions (such as substrate temperature, deposition rate, and gas flow ratios) to achieve the desired thickness-gradient profile. By adjusting these process parameters, the manufacturing method produces the complex three-dimensional film structure through conventional deposition techniques, thereby reducing manufacturing complexity compared to requiring advanced lithography or multi-step fabrication processes
3Reliability
If a thickness-gradient semiconductor film is formed to reduce channel resistance, then carrier transport improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies self-service by designing a deposition process where the thickness gradient forms automatically through controlled condensation dynamics. The process utilizes the natural tendency of vapor deposition to create varying film thicknesses based on local surface conditions and deposition parameters, eliminating the need for complex post-deposition processing or multiple fabrication steps to achieve the desired thickness profile
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration effectively reduces channel resistance and improves field-effect mobility by ensuring a thicker semiconductor film on desired portions, addressing the limitations of existing thin film transistors.
Implementation Method 1
semiconductor crystalline nuclei which are formed on the gate insulating film and the interlayer insulating film and contain at least germanium (Ge)
Implementation Method 2
a reactive thermal chemical vapor deposition (CVD) method which can form crystalline nuclei directly on an insulating film at a temperature of about 500° C. by using a redox reaction of source gases
Implementation Method 3
by using a redox reaction of source gases
Data Source
AI summary
A bottom gate-type thin film transistor includes a gate insulating film, an interlayer insulating film formed on the gate insulating film, having an opening which is formed in a formation region of a gate electrode, and a semiconductor film formed on the interlayer insulating film so as to cover the opening. The interlayer insulating film contains nitrides in an amount larger than that in the gate insulating film, and the semiconductor film includes a microcrystalline semiconductor film or a polycrystalline semiconductor film formed on semiconductor crystalline nuclei which are formed on the gate insulating film and the interlayer insulating film and contain at least Ge.